Inventor · disambiguated record
Mauricio Calle
Also filed as: CALLE MAURICIO
14 granted patents·1 pending application·194 citations·filing 1997–2013
93Inventor score
Top patents by PatentIndex Score
15 records- 0192US8497694B2On-chip sensor for measuring dynamic power supply noise of the semiconductor chipCHUA-EOAN LEW·Filed 2010·Granted Jul 30, 2013·19 cites·24 claims
- 0284US6839797B2Multi-bank scheduling to improve performance on tree accesses in a DRAM based random access memory subsystemAGERE SYSTEMS INC·Filed 2001·Granted Jan 4, 2005·39 cites·13 claims
- 0378US6944731B2Dynamic random access memory system with bank conflict avoidance featureAGERE SYSTEMS INC·Filed 2001·Granted Sep 13, 2005·26 cites·18 claims
- 0468US6804692B2Method and apparatus for reassembly of data blocks within a network processorAGERE SYSTEMS INC·Filed 2001·Granted Oct 12, 2004·14 cites·25 claims
- 0565US7088719B2Processor with packet processing order maintenance based on packet flow identifiersAGERE SYSTEMS INC·Filed 2001·Granted Aug 8, 2006·13 cites·18 claims
- 0663US6915480B2Processor with packet data flushing featureAGERE SYSTEMS INC·Filed 2001·Granted Jul 5, 2005·12 cites·20 claims
- 0762US7246102B2Method of improving the lookup performance of three-type knowledge base searchesAGERE SYSTEMS INC·Filed 2001·Granted Jul 17, 2007·20 cites·34 claims
- 0860US7079539B2Method and apparatus for classification of packet data prior to storage in processor buffer memoryAGERE SYSTEMS INC·Filed 2001·Granted Jul 18, 2006·7 cites·17 claims
- 0960US7043544B2Processor with multiple-pass non-sequential packet classification featureAGERE SYSTEMS INC·Filed 2001·Granted May 9, 2006·7 cites·18 claims
- 1051US2013285696A1On-chip sensor for measuring dynamic power supply noise of the semiconductor chipQUALCOMM INC·Filed 2013·Application pending·0 cites
- 1146US8782287B2Methods and apparatus for using multiple reassembly memories for performing multiple functionsBOUCHARD GREGG A·Filed 2001·Granted Jul 15, 2014·1 cites·20 claims
- 1243US6061775AApparatus and method for predicting a first microcode instruction of a cache line and using predecode instruction data to identify instruction boundaries and typesADVANCED MICRO DEVICES INC·Filed 1997·Granted May 9, 2000·16 cites·18 claims
- 1341US7113518B2Processor with reduced memory requirements for high-speed routing and switching of packetsAGERE SYSTEMS INC·Filed 2001·Granted Sep 26, 2006·0 cites·21 claims
- 1440US5890006AApparatus for extracting instruction specific bytes from an instructionADVANCED MICRO DEVICES INC·Filed 1997·Granted Mar 30, 1999·14 cites·22 claims
- 1533US6134650AApparatus and method for predicting a first scanned instruction as microcode instruction prior to scanning predecode dataADVANCED MICRO DEVICES INC·Filed 1997·Granted Oct 17, 2000·6 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →