Inventor · disambiguated record
Matthew A. Fisch
Also filed as: FISCH MATTHEW · FISCH MATTHEW A
33 granted patents·1,269 citations·filing 1994–2003
98Inventor score
Files withINTEL CORP33
Top patents by PatentIndex Score
33 records- 0194US6208180B1Core clock correction in a 2/N mode clocking schemeINTEL CORP·Filed 1998·Granted Mar 27, 2001·181 cites·15 claims
- 0289US6668309B2Snoop blocking for cache coherencyINTEL CORP·Filed 2003·Granted Dec 23, 2003·48 cites·11 claims
- 0384US5581782AComputer system with distributed bus arbitration scheme for symmetric and priority agentsINTEL CORP·Filed 1995·Granted Dec 3, 1996·117 cites·48 claims
- 0484US5551005AApparatus and method of handling race conditions in mesi-based multiprocessor system with private cachesINTEL CORP·Filed 1994·Granted Aug 27, 1996·102 cites·22 claims
- 0583US6268749B1Core clock correction in a 2/n mode clocking schemeINTEL CORP·Filed 2000·Granted Jul 31, 2001·28 cites·21 claims
- 0682US6006299AApparatus and method for caching lock conditions in a multi-processor systemINTEL CORP·Filed 1994·Granted Dec 21, 1999·94 cites·15 claims
- 0776US6578116B2Snoop blocking for cache coherencyINTEL CORP·Filed 2002·Granted Jun 10, 2003·18 cites·10 claims
- 0873US5774700AMethod and apparatus for determining the timing of snoop windows in a pipelined busINTEL CORP·Filed 1995·Granted Jun 30, 1998·56 cites·29 claims
- 0971US5572703AMethod and apparatus for snoop stretching using signals that convey snoop resultsINTEL CORP·Filed 1994·Granted Nov 5, 1996·47 cites·40 claims
- 1070US5682516AComputer system that maintains system wide cache coherency during deferred communication transactionsINTEL CORP·Filed 1994·Granted Oct 28, 1997·58 cites·38 claims
- 1167US5572702AMethod and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistencyINTEL CORP·Filed 1994·Granted Nov 5, 1996·40 cites·30 claims
- 1266US5548733AMethod and apparatus for dynamically controlling the current maximum depth of a pipe lined computer bus systemINTEL CORP·Filed 1994·Granted Aug 20, 1996·34 cites·31 claims
- 1363US5764934AProcessor subsystem for use with a universal computer architectureINTEL CORP·Filed 1996·Granted Jun 9, 1998·41 cites·18 claims
- 1462US5797026AMethod and apparatus for self-snooping a bus during a boundary transactionINTEL CORP·Filed 1997·Granted Aug 18, 1998·41 cites·30 claims
- 1561US6216208B1Prefetch queue responsive to read request sequencesINTEL CORP·Filed 1997·Granted Apr 10, 2001·39 cites·14 claims
- 1661US5802132AApparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking schemeINTEL CORP·Filed 1996·Granted Sep 1, 1998·33 cites·22 claims
- 1761US5535345AMethod and apparatus for sequencing misaligned external bus transactions in which the order of completion of corresponding split transaction requests is guaranteedINTEL CORP·Filed 1994·Granted Jul 9, 1996·43 cites·20 claims
- 1859US6078981ATransaction stall technique to prevent livelock in multiple-processor systemsINTEL CORP·Filed 1997·Granted Jun 20, 2000·33 cites·15 claims
- 1959US5845107ASignaling protocol conversion between a processor and a high-performance system busINTEL CORP·Filed 1996·Granted Dec 1, 1998·36 cites·16 claims
- 2054US5515516AInitialization mechanism for symmetric arbitration agentsINTEL CORP·Filed 1994·Granted May 7, 1996·22 cites·41 claims
- 2149US5909699AMethod and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistencyINTEL CORP·Filed 1996·Granted Jun 1, 1999·19 cites·24 claims
- 2246US6009477ABus agent providing dynamic pipeline depth controlINTEL CORP·Filed 1998·Granted Dec 28, 1999·17 cites·3 claims
- 2346US5784579AMethod and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depthINTEL CORP·Filed 1996·Granted Jul 21, 1998·18 cites·11 claims
- 2446US5778441AMethod and apparatus for accessing split lock variables in a computer systemINTEL CORP·Filed 1996·Granted Jul 7, 1998·18 cites·11 claims
- 2543US6460119B1Snoop blocking for cache coherencyINTEL CORP·Filed 1998·Granted Oct 1, 2002·11 cites·14 claims
- 2642US5896513AComputer system providing a universal architecture adaptive to a variety of processor types and bus protocolsINTEL CORP·Filed 1996·Granted Apr 20, 1999·14 cites·20 claims
- 2742US5834956ACore clock correction in a 2/N mode clocking schemeINTEL CORP·Filed 1996·Granted Nov 10, 1998·11 cites·12 claims
- 2841US6209068B1Read line buffer and signaling protocol for processorINTEL CORP·Filed 1997·Granted Mar 27, 2001·12 cites·12 claims
- 2940US6114887AApparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking schemeINTEL CORP·Filed 1997·Granted Sep 5, 2000·10 cites·24 claims
- 3040US5901297AInitialization mechanism for symmetric arbitration agentsINTEL CORP·Filed 1997·Granted May 4, 1999·9 cites·6 claims
- 3137US5826067AMethod and apparatus for preventing logic glitches in a 2/n clocking schemeINTEL CORP·Filed 1996·Granted Oct 20, 1998·9 cites·19 claims
- 3236US5948088ABus system providing dynamic control of pipeline depth for a multi-agent computerINTEL CORP·Filed 1997·Granted Sep 7, 1999·5 cites·14 claims
- 3335US5761449ABus system providing dynamic control of pipeline depth for a multi-agent computerINTEL CORP·Filed 1997·Granted Jun 2, 1998·5 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →