Inventor · disambiguated record
Markus Forsberg
Also filed as: FORSBERG MARKUS
8 granted patents·1 pending application·23 citations·filing 2007–2015
80Inventor score
Top patents by PatentIndex Score
9 records- 0184US7547610B2Method of making a semiconductor device comprising isolation trenches inducing different types of strainADVANCED MICRO DEVICES INC·Filed 2007·Granted Jun 16, 2009·11 cites·12 claims
- 0281US8796807B2Temperature monitoring in a semiconductor device by using a PN junction based on silicon/germanium materialsSTEPHAN ROLF·Filed 2011·Granted Aug 5, 2014·8 cites·6 claims
- 0362US8097519B2SOI device having a substrate diode formed by reduced implantation energyWIATR MACIEJ·Filed 2008·Granted Jan 17, 2012·3 cites·13 claims
- 0456US8138571B2Semiconductor device comprising isolation trenches inducing different types of strainSCHWAN CHRISTOPH·Filed 2009·Granted Mar 20, 2012·1 cites·14 claims
- 0549US9023712B2Method for self-aligned removal of a high-K gate dielectric above an STI regionWEI ANDY·Filed 2008·Granted May 5, 2015·0 cites·20 claims
- 0648US9659928B2Semiconductor device having a high-K gate dielectric above an STI regionADVANCED MICRO DEVICES INC·Filed 2015·Granted May 23, 2017·0 cites·20 claims
- 0743US2009218601A1Temperature monitoring in a semiconductor device by using an pn junction based on silicon/germanium materialSTEPHAN ROLF·Filed 2008·Application pending·0 cites
- 0841US8101512B2Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topographyGERHARDT MARTIN·Filed 2007·Granted Jan 24, 2012·0 cites·20 claims
- 0937US8334573B2Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devicesWIATR MACIEJ·Filed 2010·Granted Dec 18, 2012·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →