Inventor · disambiguated record
Mark J. French
Also filed as: FRENCH MARK · FRENCH MARK J
23 granted patents·2 pending applications·381 citations·filing 2004–2015
96Inventor score
Top patents by PatentIndex Score
25 records- 0196US8228328B1Early Z testing for multiple render targetsFRENCH MARK J·Filed 2007·Granted Jul 24, 2012·53 cites·20 claims
- 0295US7830392B1Connecting multiple pixel shaders to a frame buffer without a crossbarNVIDIA CORP·Filed 2006·Granted Nov 9, 2010·16 cites·10 claims
- 0395US7626588B1Prescient cache managementNVIDIA CORP·Filed 2006·Granted Dec 1, 2009·24 cites·20 claims
- 0494US8233004B1Color-compression using automatic reduction of multi-sampled pixelsMOLNAR STEVEN E·Filed 2006·Granted Jul 31, 2012·42 cites·16 claims
- 0594US8207975B1Graphics rendering pipeline that supports early-Z and late-Z virtual machinesMOLNAR STEVEN E·Filed 2007·Granted Jun 26, 2012·43 cites·20 claims
- 0693US7692659B1Color-compression using automatic reduction of multi-sampled pixelsNVIDIA CORP·Filed 2006·Granted Apr 6, 2010·36 cites·20 claims
- 0790US8730249B2Parallel array architecture for a graphics processorDANSKIN JOHN M·Filed 2011·Granted May 20, 2014·6 cites·17 claims
- 0890US7382368B1Planar z representation for z compressionNVIDIA CORP·Filed 2004·Granted Jun 3, 2008·61 cites·12 claims
- 0989US7616209B1Prescient cache managementNVIDIA CORP·Filed 2006·Granted Nov 10, 2009·9 cites·20 claims
- 1088US7999820B1Methods and systems for reusing memory addresses in a graphics systemNVIDIA CORP·Filed 2007·Granted Aug 16, 2011·20 cites·22 claims
- 1183US7519797B1Hierarchical multi-precision pipeline countersNIVIDIA CORP·Filed 2006·Granted Apr 14, 2009·22 cites·9 claims
- 1280US8059128B1Apparatus and method for performing blit operations across parallel processorsLEGAKIS JUSTIN S·Filed 2006·Granted Nov 15, 2011·5 cites·5 claims
- 1379US8085272B1Method and system for improving data coherency in a parallel rendering systemMOLNAR STEVEN E·Filed 2006·Granted Dec 27, 2011·10 cites·14 claims
- 1478US7944452B1Methods and systems for reusing memory addresses in a graphics systemNVIDIA CORP·Filed 2006·Granted May 17, 2011·11 cites·20 claims
- 1576US8243069B1Late Z testing for multiple render targetsFRENCH MARK J·Filed 2007·Granted Aug 14, 2012·6 cites·21 claims
- 1673US7880747B1Blend optimizations that are conformant to floating-point rulesNVIDIA CORP·Filed 2006·Granted Feb 1, 2011·2 cites·16 claims
- 1773US7768519B1High-performance crossbar for high throughput pipelinesNVIDIA CORP·Filed 2006·Granted Aug 3, 2010·6 cites·20 claims
- 1864US7917736B1Latency tolerant pipeline synchronizationNVIDIA CORP·Filed 2009·Granted Mar 29, 2011·2 cites·15 claims
- 1964US7620798B1Latency tolerant pipeline synchronizationNVIDIA CORP·Filed 2006·Granted Nov 17, 2009·2 cites·10 claims
- 2062US8933933B2Optimizing a graphics rendering pipeline using early Z-modeFRENCH MARK J·Filed 2006·Granted Jan 13, 2015·3 cites·20 claims
- 2162US8232991B1Z-test result reconciliation with multiple partitionsFRENCH MARK J·Filed 2007·Granted Jul 31, 2012·2 cites·20 claims
- 2258US2007159488A1Parallel Array Architecture for a Graphics ProcessorNVIDIA CORP·Filed 2006·Application pending·0 cites
- 2343US2015326480A1Conditional action following tcam filtersALCATEL LUCENT·Filed 2014·Application pending·0 cites
- 2442US9385242B2Semiconductor diode assemblyDIODES INC·Filed 2015·Granted Jul 5, 2016·0 cites·15 claims
- 2542US9048106B2Semiconductor diode assemblyDIODES INC·Filed 2012·Granted Jun 2, 2015·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →