Inventor · disambiguated record
Marcel Gort
Also filed as: GORT MARCEL · GORT MARCEL PETER
7 granted patents·3 pending applications·5 citations·filing 2001–2024
74Inventor score
Top patents by PatentIndex Score
10 records- 0177US12052160B2FPGA neighbor output mux direct connections to minimize routing hopsEFINIX INC·Filed 2022·Granted Jul 30, 2024·1 cites·26 claims
- 0277US11791823B2FPGA inter-tile control signal sharingEFINIX INC·Filed 2022·Granted Oct 17, 2023·1 cites·18 claims
- 0376US12301232B2FPGA inter-tile control signal sharingEFINIX INC·Filed 2023·Granted May 13, 2025·0 cites·18 claims
- 0465US12101092B2Chained programmable delay elementsEFINIX INC·Filed 2023·Granted Sep 24, 2024·0 cites·20 claims
- 0563US2024380684A1Fpga neighbor output mux direct connections to minimize routing hopsEFINIX INC·Filed 2024·Application pending·0 cites
- 0658US11757439B2Chained programmable delay elementsEFINIX INC·Filed 2022·Granted Sep 12, 2023·0 cites·18 claims
- 0751US7033103B2Marking assembly for the marking of particular traffic situations and objectsGORT MARCEL PETER·Filed 2001·Granted Apr 25, 2006·3 cites·22 claims
- 0841US11791821B2Fast FPGA interconnect stitching for wire highwaysEFINIX INC·Filed 2022·Granted Oct 17, 2023·0 cites·16 claims
- 0940US2022244912A1Dynamic block size carry-skip adder construction on fpgas by combining ripple carry adders with routable propagate/generate signalsEFINIX INC·Filed 2021·Application pending·0 cites
- 1040US2022245315A1Dynamic fpga logic capacity based on accurate early routability estimationEFINIX INC·Filed 2021·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →