Inventor · disambiguated record
Matthew T. Guzowski
Also filed as: GUZOWSKI MATTHEW T · GUZOWSKI MATTHEW THOMAS
13 granted patents·6 pending applications·96 citations·filing 2005–2024
90Inventor score
Top patents by PatentIndex Score
19 records- 0195US9158885B1Reducing color conflicts in triple patterning lithographyIBM·Filed 2014·Granted Oct 13, 2015·52 cites·20 claims
- 0290US11308257B1Stacked via rivets in chip hotspotsIBM·Filed 2020·Granted Apr 19, 2022·2 cites·17 claims
- 0384US8627247B1Systems and methods for fixing pin mismatch in layout migrationMCCULLEN KEVIN W·Filed 2012·Granted Jan 7, 2014·10 cites·20 claims
- 0479US9971861B2Selective boundary overlay insertion for hierarchical circuit designIBM·Filed 2016·Granted May 15, 2018·3 cites·14 claims
- 0573US7275229B2Auto connection assignment system and methodIBM·Filed 2005·Granted Sep 25, 2007·7 cites·24 claims
- 0670US7895562B2Adaptive weighting method for layout optimization with multiple prioritiesIBM·Filed 2007·Granted Feb 22, 2011·5 cites·6 claims
- 0769US7735042B2Context aware sub-circuit layout modificationIBM·Filed 2007·Granted Jun 8, 2010·4 cites·20 claims
- 0865US7865848B2Layout optimization using parameterized cellsIBM·Filed 2007·Granted Jan 4, 2011·3 cites·2 claims
- 0964US7568173B2Independent migration of hierarchical designs with methods of finding and fixing opens during migrationIBM·Filed 2007·Granted Jul 28, 2009·3 cites·12 claims
- 1064US7490308B2Method for implementing overlay-based modification of VLSI design layoutIBM·Filed 2006·Granted Feb 10, 2009·4 cites·6 claims
- 1163US7765509B2Auto connection assignment system and methodIBM·Filed 2007·Granted Jul 27, 2010·3 cites·20 claims
- 1259US12271674B2Generating a power delivery network based on the routing of signal wires within a circuit designIBM·Filed 2022·Granted Apr 8, 2025·0 cites·17 claims
- 1355US2025245413A1Timing-aware fillIBM·Filed 2024·Application pending·0 cites
- 1453US2025190662A1Translation of integrated circuit design data into a production formatIBM·Filed 2023·Application pending·0 cites
- 1551US2024411975A1Density-aware fill with boundary compensationIBM·Filed 2023·Application pending·0 cites
- 1650US2025245409A1Retargeting-aware fillIBM·Filed 2024·Application pending·0 cites
- 1748US7752589B2Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit designIBM·Filed 2007·Granted Jul 6, 2010·0 cites·32 claims
- 1844US2009037850A1Polygonal area design rule correction method for vlsi layoutsGRAY MICHAEL S·Filed 2007·Application pending·0 cites
- 1939US2012233576A1Schematic-based layout migrationBARROWS GEOFFREY R·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →