Inventor · disambiguated record
Mattheus Cornelis Antonius Adrianus Heddes
Also filed as: HEDDES MATTHEUS · HEDDES MATTHEUS C · HEDDES MATTHEUS C A · HEDDES MATTHEUS CORNELIS ANTONIUS ADRIANUS
24 granted patents·6 pending applications·173 citations·filing 1993–2023
93Inventor score
Top patents by PatentIndex Score
30 records- 0195US5450351AContent addressable memory implementation with random access memoryIBM·Filed 1993·Granted Sep 12, 1995·142 cites·9 claims
- 0291US11989414B2Method and apparatus for compressing and decompressing sparse data setsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2023·Granted May 21, 2024·2 cites·20 claims
- 0391US11720252B1Method and apparatus for compressing and decompressing sparse data setsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Aug 8, 2023·2 cites·20 claims
- 0487US11886938B2Message communication between integrated computing devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Jan 30, 2024·2 cites·20 claims
- 0584US10747501B2Providing efficient floating-point operations using matrix processors in processor-based systemsQUALCOMM INC·Filed 2018·Granted Aug 18, 2020·4 cites·20 claims
- 0683US10725740B2Providing efficient multiplication of sparse matrices in matrix-processor-based devicesQUALCOMM INC·Filed 2018·Granted Jul 28, 2020·5 cites·12 claims
- 0781US10236917B2Providing memory bandwidth compression in chipkill-correct memory architecturesQUALCOMM INC·Filed 2016·Granted Mar 19, 2019·4 cites·24 claims
- 0880US9740621B2Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methodsQUALCOMM INC·Filed 2015·Granted Aug 22, 2017·3 cites·28 claims
- 0977US10936943B2Providing flexible matrix processors for performing neural network convolution in matrix-processor-based devicesQUALCOMM INC·Filed 2018·Granted Mar 2, 2021·3 cites·20 claims
- 1076US10176096B2Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator cachesQUALCOMM INC·Filed 2016·Granted Jan 8, 2019·2 cites·47 claims
- 1172US10146693B2Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based systemQUALCOMM INC·Filed 2017·Granted Dec 4, 2018·1 cites·15 claims
- 1269US10191850B2Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based systemQUALCOMM INC·Filed 2016·Granted Jan 29, 2019·1 cites·22 claims
- 1368US10176090B2Providing memory bandwidth compression using adaptive compression in central processing unit (CPU)-based systemsQUALCOMM INC·Filed 2016·Granted Jan 8, 2019·1 cites·33 claims
- 1465US10838862B2Memory controllers employing memory capacity compression, and related processor-based systems and methodsQUALCOMM INC·Filed 2015·Granted Nov 17, 2020·1 cites·28 claims
- 1554US11580388B2Distributed processing architectureMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Feb 14, 2023·0 cites·28 claims
- 1654US10152261B2Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based systemQUALCOMM INC·Filed 2017·Granted Dec 11, 2018·0 cites·7 claims
- 1753US11848689B2Method and apparatus for compression multiplexing for sparse computationsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Dec 19, 2023·0 cites·20 claims
- 1853US10067706B2Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based systemQUALCOMM INC·Filed 2016·Granted Sep 4, 2018·0 cites·29 claims
- 1953US2023334284A1Sparsifying vectors for neural network models based on overlapping windowsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Application pending·0 cites
- 2052US11942970B2Compression circuits and methods using tree based encoding of bit masksMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Mar 26, 2024·0 cites·20 claims
- 2149US11076210B1Distributed processing architectureMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jul 27, 2021·0 cites·18 claims
- 2248US12511516B2Training neural networks based on dual pipeline architecturesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Dec 30, 2025·0 cites·16 claims
- 2346US10055158B2Providing flexible management of heterogeneous memory systems using spatial quality of service (QoS) tagging in processor-based systemsQUALCOMM INC·Filed 2016·Granted Aug 21, 2018·0 cites·25 claims
- 2445US10503661B2Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based systemQUALCOMM INC·Filed 2015·Granted Dec 10, 2019·0 cites·16 claims
- 2545US10467092B2Providing space-efficient storage for dynamic random access memory (DRAM) cache tagsQUALCOMM INC·Filed 2016·Granted Nov 5, 2019·0 cites·22 claims
- 2643US2019079903A1Providing matrix multiplication using vector registers in processor-based devicesQUALCOMM INC·Filed 2018·Application pending·0 cites
- 2742US2022244911A1Digital circuitry for normalization functionsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Application pending·0 cites
- 2841US2022405571A1Sparsifying narrow data formats for neural networksMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Application pending·0 cites
- 2940US2017212840A1Providing scalable dynamic random access memory (dram) cache management using tag directory cachesQUALCOMM INC·Filed 2016·Application pending·0 cites
- 3037US2016224241A1PROVIDING MEMORY BANDWIDTH COMPRESSION USING BACK-TO-BACK READ OPERATIONS BY COMPRESSED MEMORY CONTROLLERS (CMCs) IN A CENTRAL PROCESSING UNIT (CPU)-BASED SYSTEMQUALCOMM INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →