Inventor · disambiguated record
Marek Hytha
Also filed as: HYTHA MAREK
69 granted patents·35 pending applications·3,887 citations·filing 2003–2025
99Inventor score
Top patents by PatentIndex Score
104 records- 0199US11978771B2Gate-all-around (GAA) device including a superlatticeATOMERA INC·Filed 2022·Granted May 7, 2024·7 cites·21 claims
- 0299US11848356B2Method for making semiconductor device including superlattice with oxygen and carbon monolayersATOMERA INC·Filed 2021·Granted Dec 19, 2023·6 cites·21 claims
- 0399US11837634B2Semiconductor device including superlattice with oxygen and carbon monolayersATOMERA INC·Filed 2021·Granted Dec 5, 2023·10 cites·21 claims
- 0499US11728385B2Semiconductor device including superlattice with O18 enriched monolayersATOMERA INC·Filed 2021·Granted Aug 15, 2023·7 cites·24 claims
- 0599US11721546B2Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atomsATOMERA INC·Filed 2021·Granted Aug 8, 2023·6 cites·20 claims
- 0699US11430869B2Method for making superlattice structures with reduced defect densitiesATOMERA INC·Filed 2020·Granted Aug 30, 2022·8 cites·13 claims
- 0799US10593761B1Method for making a semiconductor device having reduced contact resistanceATOMERA INC·Filed 2018·Granted Mar 17, 2020·51 cites·21 claims
- 0899US10580866B1Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Mar 3, 2020·49 cites·21 claims
- 0999US10453945B2Semiconductor device including resonant tunneling diode structure having a superlatticeATOMERA INC·Filed 2017·Granted Oct 22, 2019·45 cites·23 claims
- 1099US10361243B2Method for making CMOS image sensor including superlattice to enhance infrared light absorptionATOMERA INC·Filed 2017·Granted Jul 23, 2019·44 cites·20 claims
- 1199US10276625B1CMOS image sensor including superlattice to enhance infrared light absorptionATOMERA INC·Filed 2017·Granted Apr 30, 2019·54 cites·20 claims
- 1299US10249745B2Method for making a semiconductor device including a resonant tunneling diode structure having a superlatticeATOMERA INC·Filed 2017·Granted Apr 2, 2019·52 cites·22 claims
- 1399US10170604B2Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layersATOMERA INC·Filed 2017·Granted Jan 1, 2019·60 cites·20 claims
- 1499US10170603B2Semiconductor device including a resonant tunneling diode structure with electron mean free path control layersATOMERA INC·Filed 2017·Granted Jan 1, 2019·61 cites·20 claims
- 1599US10109479B1Method of making a semiconductor device with a buried insulating layer formed by annealing a superlatticeATOMERA INC·Filed 2017·Granted Oct 23, 2018·82 cites·23 claims
- 1699US7435988B2Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channelMEARS TECHNOLOGIES INC·Filed 2005·Granted Oct 14, 2008·110 cites·37 claims
- 1799US7303948B2Semiconductor device including MOSFET having band-engineered superlatticeMEARS TECHNOLOGIES INC·Filed 2005·Granted Dec 4, 2007·110 cites·11 claims
- 1899US7265002B2Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channelRJ MEARS LLC·Filed 2005·Granted Sep 4, 2007·114 cites·39 claims
- 1998US11923418B2Semiconductor device including a superlattice and enriched silicon 28 epitaxial layerATOMERA INC·Filed 2021·Granted Mar 5, 2024·7 cites·24 claims
- 2098US11810784B2Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layerATOMERA INC·Filed 2021·Granted Nov 7, 2023·9 cites·27 claims
- 2198US11682712B2Method for making semiconductor device including superlattice with O18 enriched monolayersATOMERA INC·Filed 2021·Granted Jun 20, 2023·7 cites·24 claims
- 2298US11631584B1Method for making semiconductor device with selective etching of superlattice to define etch stop layerATOMERA INC·Filed 2021·Granted Apr 18, 2023·7 cites·20 claims
- 2398US10868120B1Method for making a varactor with hyper-abrupt junction region including a superlatticeATOMERA INC·Filed 2019·Granted Dec 15, 2020·31 cites·25 claims
- 2498US10854717B2Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Dec 1, 2020·32 cites·20 claims
- 2598US10847618B2Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistanceATOMERA INC·Filed 2018·Granted Nov 24, 2020·33 cites·20 claims
- 2698US10840337B2Method for making a FINFET having reduced contact resistanceATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·21 claims
- 2798US10840336B2Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methodsATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·17 claims
- 2898US10840335B2Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistanceATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·23 claims
- 2998US10840388B1Varactor with hyper-abrupt junction region including a superlatticeATOMERA INC·Filed 2019·Granted Nov 17, 2020·33 cites·23 claims
- 3098US10825901B1Semiconductor devices including hyper-abrupt junction region including a superlatticeATOMERA INC·Filed 2019·Granted Nov 3, 2020·32 cites·17 claims
- 3198US10825902B1Varactor with hyper-abrupt junction region including spaced-apart superlatticesATOMERA INC·Filed 2019·Granted Nov 3, 2020·30 cites·22 claims
- 3298US10818755B2Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Oct 27, 2020·33 cites·21 claims
- 3398US10811498B2Method for making superlattice structures with reduced defect densitiesATOMERA INC·Filed 2018·Granted Oct 20, 2020·35 cites·16 claims
- 3498US10727049B2Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlatticeATOMERA INC·Filed 2018·Granted Jul 28, 2020·30 cites·25 claims
- 3598US10580867B1FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistanceATOMERA INC·Filed 2018·Granted Mar 3, 2020·49 cites·22 claims
- 3698US10566191B1Semiconductor device including superlattice structures with reduced defect densitiesATOMERA INC·Filed 2018·Granted Feb 18, 2020·51 cites·22 claims
- 3798US10468245B2Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlatticeATOMERA INC·Filed 2018·Granted Nov 5, 2019·46 cites·25 claims
- 3898US8389974B2Multiple-wavelength opto-electronic device including a superlatticeMEARS ROBERT J·Filed 2011·Granted Mar 5, 2013·109 cites·34 claims
- 3998US7880161B2Multiple-wavelength opto-electronic device including a superlatticeMEARS TECHNOLOGIES INC·Filed 2007·Granted Feb 1, 2011·121 cites·25 claims
- 4098US7863066B2Method for making a multiple-wavelength opto-electronic device including a superlatticeMEARS TECHNOLOGIES INC·Filed 2007·Granted Jan 4, 2011·110 cites·25 claims
- 4198US7718996B2Semiconductor device comprising a lattice matching layerMEARS TECHNOLOGIES INC·Filed 2007·Granted May 18, 2010·110 cites·26 claims
- 4298US7700447B2Method for making a semiconductor device comprising a lattice matching layerMEARS TECHNOLOGIES INC·Filed 2007·Granted Apr 20, 2010·113 cites·28 claims
- 4398US7625767B2Methods of making spintronic devices with constrained spintronic dopantMEARS TECHNOLOGIES INC·Filed 2007·Granted Dec 1, 2009·117 cites·24 claims
- 4498US7517702B2Method for making an electronic device including a poled superlattice having a net electrical dipole momentMEARS TECHNOLOGIES INC·Filed 2006·Granted Apr 14, 2009·130 cites·27 claims
- 4598US7446002B2Method for making a semiconductor device comprising a superlattice dielectric interface layerMEARS TECHNOLOGIES INC·Filed 2005·Granted Nov 4, 2008·120 cites·21 claims
- 4698US7153763B2Method for making a semiconductor device including band-engineered superlattice using intermediate annealingRJ MEARS LLC·Filed 2005·Granted Dec 26, 2006·119 cites·31 claims
- 4798US7071119B2Method for making a semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structureRJ MEARS LLC·Filed 2004·Granted Jul 4, 2006·112 cites·26 claims
- 4898US7034329B2Semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structureRJ MEARS LLC·Filed 2004·Granted Apr 25, 2006·114 cites·26 claims
- 4998US6958486B2Semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted Oct 25, 2005·114 cites·71 claims
- 5098US6952018B2Semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted Oct 4, 2005·112 cites·26 claims
Showing the top 50 of 104 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →