Inventor · disambiguated record
Manoj Khare
Also filed as: KHARE MANOJ
17 granted patents·5 pending applications·637 citations·filing 1992–2007
96Inventor score
Technology areasG06F
Top patents by PatentIndex Score
22 records- 0192US6971098B2Method and apparatus for managing transaction requests in a multi-node architectureINTEL CORP·Filed 2001·Granted Nov 29, 2005·88 cites·29 claims
- 0292US6615319B2Distributed mechanism for resolving cache coherence conflicts in a multi-node computer architectureINTEL CORP·Filed 2000·Granted Sep 2, 2003·95 cites·21 claims
- 0392US6487643B1Method and apparatus for preventing starvation in a multi-node architectureINTEL CORP·Filed 2000·Granted Nov 26, 2002·83 cites·24 claims
- 0491US7464254B2Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to dataCISCO TECH INC·Filed 2004·Granted Dec 9, 2008·77 cites·25 claims
- 0590US6810467B1Method and apparatus for centralized snoop filteringINTEL CORP·Filed 2000·Granted Oct 26, 2004·72 cites·16 claims
- 0687US6842830B2Mechanism for handling explicit writeback in a cache coherent multi-node architectureINTEL CORP·Filed 2001·Granted Jan 11, 2005·39 cites·9 claims
- 0782US7996625B2Method and apparatus for reducing memory latency in a cache coherent multi-node architectureINTEL CORP·Filed 2007·Granted Aug 9, 2011·10 cites·8 claims
- 0881US7085918B2Methods and apparatuses for evaluation of regular expressions of arbitrary sizeCISCO TECH INC·Filed 2004·Granted Aug 1, 2006·32 cites·12 claims
- 0980US7234029B2Method and apparatus for reducing memory latency in a cache coherent multi-node architectureINTEL CORP·Filed 2000·Granted Jun 19, 2007·27 cites·27 claims
- 1079US7124252B1Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor systemINTEL CORP·Filed 2000·Granted Oct 17, 2006·28 cites·26 claims
- 1176US6772298B2Method and apparatus for invalidating a cache line without data return in a multi-node architectureINTEL CORP·Filed 2000·Granted Aug 3, 2004·24 cites·19 claims
- 1269US6859864B2Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache lineINTEL CORP·Filed 2000·Granted Feb 22, 2005·14 cites·19 claims
- 1367US7167957B2Mechanism for handling explicit writeback in a cache coherent multi-node architectureINTEL CORP·Filed 2004·Granted Jan 23, 2007·9 cites·11 claims
- 1465US6826619B1Method and apparatus for preventing starvation in a multi-node architectureINTEL CORP·Filed 2000·Granted Nov 30, 2004·11 cites·21 claims
- 1557US6976129B2Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architectureINTEL CORP·Filed 2002·Granted Dec 13, 2005·5 cites·21 claims
- 1656US6622215B2Mechanism for handling conflicts in a multi-node computer architectureINTEL CORP·Filed 2000·Granted Sep 16, 2003·4 cites·15 claims
- 1749US2006106993A1Mechanism for handling explicit writeback in a cache coherent multi-node architectureKHARE MANOJ·Filed 2005·Application pending·0 cites
- 1847US5367657AMethod and apparatus for efficient read prefetching of instruction code data in computer memory subsystemsINTEL CORP·Filed 1992·Granted Nov 22, 1994·19 cites·10 claims
- 1941US2002087775A1Apparatus and method for interrupt deliveryFiled 2000·Application pending·0 cites
- 2041US2002087765A1Method and system for completing purge requests or the like in a multi-node multiprocessor systemFiled 2000·Application pending·0 cites
- 2140US2003131201A1Mechanism for efficiently supporting the full MESI (modified, exclusive, shared, invalid) protocol in a cache coherent multi-node shared memory systemFiled 2000·Application pending·0 cites
- 2238US2002087766A1Method and apparatus to implement a locked-bus transactionFiled 2000·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →