Inventor · disambiguated record
Marc D. Knox
Also filed as: KNOX MARC · KNOX MARC D · KNOX MARC DOUGLAS
20 granted patents·3 pending applications·149 citations·filing 1998–2019
94Inventor score
Top patents by PatentIndex Score
23 records- 0187US10261108B2Low force wafer test probe with variable geometryIBM·Filed 2016·Granted Apr 16, 2019·3 cites·21 claims
- 0284US8854073B2Methods and apparatus for margin testing integrated circuits using asynchronously timed varied supply voltage and test patternsGROSCH DAVID A·Filed 2011·Granted Oct 7, 2014·9 cites·25 claims
- 0384US7259580B2Method and apparatus for temporary thermal coupling of an electronic device to a heat sink during testIBM·Filed 2005·Granted Aug 21, 2007·15 cites·17 claims
- 0478US7759960B2Integrated circuit testing methods using well bias modificationIBM·Filed 2008·Granted Jul 20, 2010·7 cites·24 claims
- 0576US7400162B2Integrated circuit testing methods using well bias modificationIBM·Filed 2003·Granted Jul 15, 2008·17 cites·6 claims
- 0675US11322473B2Interconnect and tuning thereofIBM·Filed 2019·Granted May 3, 2022·2 cites·13 claims
- 0774US7567090B2Liquid recovery, collection method and apparatus in a non-recirculating test and burn-in applicationIBM·Filed 2006·Granted Jul 28, 2009·9 cites·20 claims
- 0874US7564256B2Integrated circuit testing methods using well bias modificationINTERNAT BUSINESS MACHINES COM·Filed 2008·Granted Jul 21, 2009·6 cites·2 claims
- 0973US6504392B2Actively controlled heat sink for convective burn-in ovenIBM·Filed 1999·Granted Jan 7, 2003·38 cites·43 claims
- 1070US6577146B2Method of burning in an integrated circuit chip packageIBM·Filed 2001·Granted Jun 10, 2003·16 cites·6 claims
- 1168US7486098B2Integrated circuit testing method using well bias modificationIBM·Filed 2007·Granted Feb 3, 2009·4 cites·1 claims
- 1267US11029334B2Low force wafer test probeIBM·Filed 2019·Granted Jun 8, 2021·0 cites·10 claims
- 1367US9269603B2Temporary liquid thermal interface material for surface tension adhesion and thermal controlIBM·Filed 2013·Granted Feb 23, 2016·2 cites·16 claims
- 1466US10663487B2Low force wafer test probe with variable geometryIBM·Filed 2019·Granted May 26, 2020·0 cites·21 claims
- 1562US2018358323A1Pressing solder bumps to match probe profile during wafer level testingIBM·Filed 2017·Application pending·0 cites
- 1658US10444260B2Low force wafer test probeIBM·Filed 2016·Granted Oct 15, 2019·0 cites·23 claims
- 1757US6122760ABurn in technique for chips containing different types of IC circuitryIBM·Filed 1998·Granted Sep 19, 2000·20 cites·9 claims
- 1850US9437670B2Light activated test connectionsIBM·Filed 2012·Granted Sep 6, 2016·0 cites·17 claims
- 1948US11561243B2Compliant organic substrate assembly for rigid probesIBM·Filed 2019·Granted Jan 24, 2023·0 cites·16 claims
- 2048US2018358322A1Pressing solder bumps to match probe profile during wafer level testingIBM·Filed 2017·Application pending·0 cites
- 2147US2018358321A1Pressing solder bumps to match probe profile during wafer level testingIBM·Filed 2017·Application pending·0 cites
- 2241US7332927B2Apparatus for temporary thermal coupling of an electronic device to a heat sink during testIBM·Filed 2007·Granted Feb 19, 2008·0 cites·20 claims
- 2340US7265561B2Device burn in utilizing voltage controlIBM·Filed 2003·Granted Sep 4, 2007·1 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →