Inventor · disambiguated record
Mauro J. Kobrinsky
Also filed as: KOBRINSKY MAURO · KOBRINSKY MAURO J
96 granted patents·90 pending applications·945 citations·filing 2002–2025
99Inventor score
Top patents by PatentIndex Score
186 records- 0198US11616015B2Integrated circuit device with back-side interconnection to deep source/drain semiconductorINTEL CORP·Filed 2020·Granted Mar 28, 2023·3 cites·19 claims
- 0298US11087832B1Three-dimensional nanoribbon-based static random-access memoryINTEL CORP·Filed 2020·Granted Aug 10, 2021·18 cites·20 claims
- 0397US10886217B2Integrated circuit device with back-side interconnection to deep source/drain semiconductorINTEL CORP·Filed 2016·Granted Jan 5, 2021·20 cites·20 claims
- 0497US10797139B2Methods of forming backside self-aligned vias and structures formed therebyINTEL CORP·Filed 2019·Granted Oct 6, 2020·22 cites·20 claims
- 0597US8993404B2Metal-insulator-metal capacitor formation techniquesINTEL CORP·Filed 2013·Granted Mar 31, 2015·92 cites·23 claims
- 0697US7307005B2Wafer bonding with highly compliant plate having filler material enclosed hollow coreINTEL CORP·Filed 2004·Granted Dec 11, 2007·226 cites·6 claims
- 0797US6790748B2Thinning techniques for wafer-to-wafer vertical stacksINTEL CORP·Filed 2002·Granted Sep 14, 2004·242 cites·22 claims
- 0896US11799037B2Gate-all-around integrated circuit structures having asymmetric source and drain contact structuresINTEL CORP·Filed 2022·Granted Oct 24, 2023·2 cites·23 claims
- 0995US11257822B2Three-dimensional nanoribbon-based dynamic random-access memoryINTEL CORP·Filed 2019·Granted Feb 22, 2022·9 cites·26 claims
- 1095US11239238B2Thin film transistor based memory cells on both sides of a layer of logic devicesINTEL CORP·Filed 2019·Granted Feb 1, 2022·13 cites·23 claims
- 1195US10734412B2Backside contact resistance reduction for semiconductor devices with metallization on both sidesINTEL CORP·Filed 2016·Granted Aug 4, 2020·15 cites·20 claims
- 1295US10054737B2Optical I/O system using planar light-wave integrated circuitINTEL CORP·Filed 2016·Granted Aug 21, 2018·12 cites·25 claims
- 1394US11056492B1Dense memory arrays utilizing access transistors with back-side contactsINTEL CORP·Filed 2019·Granted Jul 6, 2021·9 cites·18 claims
- 1494US9391019B2Scalable interconnect structures with selective via postsINTEL CORP·Filed 2014·Granted Jul 12, 2016·26 cites·19 claims
- 1594US9036954B2Optical waveguide structureKOBRINSKY MAURO J·Filed 2011·Granted May 19, 2015·18 cites·16 claims
- 1693US11830788B2Integrated circuits and methods for forming integrated circuitsINTEL CORP·Filed 2021·Granted Nov 28, 2023·2 cites·6 claims
- 1793US11367796B2Gate-all-around integrated circuit structures having asymmetric source and drain contact structuresINTEL CORP·Filed 2018·Granted Jun 21, 2022·6 cites·25 claims
- 1893US11335686B2Transistors with back-side contacts to create three dimensional memory and logicINTEL CORP·Filed 2019·Granted May 17, 2022·8 cites·20 claims
- 1993US11139241B2Integrated circuit device with crenellated metal trace layoutINTEL CORP·Filed 2016·Granted Oct 5, 2021·6 cites·13 claims
- 2093US9507086B2Optical I/O system using planar light-wave integrated circuitKOBRINSKY MAURO J·Filed 2011·Granted Nov 29, 2016·19 cites·9 claims
- 2193US8421225B2Three-dimensional stacked substrate arrangementsRAMANATHAN SHRIRAM·Filed 2012·Granted Apr 16, 2013·14 cites·8 claims
- 2292US10367070B2Methods of forming backside self-aligned vias and structures formed therebyINTEL CORP·Filed 2015·Granted Jul 30, 2019·8 cites·21 claims
- 2391US12170273B2Integrated circuit assemblies with direct chip attach to circuit boardsINTEL CORP·Filed 2021·Granted Dec 17, 2024·2 cites·20 claims
- 2491US11139300B2Three-dimensional memory arrays with layer selector transistorsINTEL CORP·Filed 2019·Granted Oct 5, 2021·5 cites·20 claims
- 2591US9182544B2Fabrication of planar light-wave circuits (PLCS) for optical I/OKOBRINSKY MAURO J·Filed 2011·Granted Nov 10, 2015·16 cites·20 claims
- 2687US7973407B2Three-dimensional stacked substrate arrangementsINTEL CORP·Filed 2008·Granted Jul 5, 2011·12 cites·12 claims
- 2786US10497613B2Microelectronic conductive routes and methods of making the sameINTEL CORP·Filed 2015·Granted Dec 3, 2019·5 cites·14 claims
- 2886US9443922B2Metal-insulator-metal capacitor formation techniquesINTEL CORP·Filed 2015·Granted Sep 13, 2016·4 cites·20 claims
- 2985US12394716B2Integrated circuit interconnect structures with graphene capINTEL CORP·Filed 2021·Granted Aug 19, 2025·1 cites·19 claims
- 3085US11056356B1Fluid viscosity control during wafer bondingINTEL CORP·Filed 2018·Granted Jul 6, 2021·5 cites·9 claims
- 3185US10685949B2Flexible electronic system with wire bondsINTEL CORP·Filed 2017·Granted Jun 16, 2020·4 cites·18 claims
- 3285US8731346B2Waveguide integration on laser for alignment-tolerant assemblyTSENG JIA-HUNG·Filed 2012·Granted May 20, 2014·14 cites·21 claims
- 3384US12327809B2Vertically stacked and bonded memory arraysINTEL CORP·Filed 2021·Granted Jun 10, 2025·1 cites·20 claims
- 3484US11373999B2Deep trench via for three-dimensional integrated circuitINTEL CORP·Filed 2018·Granted Jun 28, 2022·3 cites·26 claims
- 3584US10553532B2Structure and method to self align via to top and bottom of tight pitch metal interconnect layersINTEL CORP·Filed 2014·Granted Feb 4, 2020·6 cites·25 claims
- 3683US12230721B2Gate-all-around integrated circuit structures having asymmetric source and drain contact structuresINTEL CORP·Filed 2023·Granted Feb 18, 2025·0 cites·21 claims
- 3783US12147083B2Hybrid manufacturing for integrating photonic and electronic componentsINTEL CORP·Filed 2020·Granted Nov 19, 2024·1 cites·21 claims
- 3883US11444166B2Backside source/drain replacement for semiconductor devices with metallization on both sidesINTEL CORP·Filed 2020·Granted Sep 13, 2022·1 cites·20 claims
- 3982US11621354B2Integrated circuit structures having partitioned source or drain contact structuresINTEL CORP·Filed 2018·Granted Apr 4, 2023·2 cites·25 claims
- 4082US11329162B2Integrated circuit structures having differentiated neighboring partitioned source or drain contact structuresINTEL CORP·Filed 2018·Granted May 10, 2022·3 cites·25 claims
- 4182US11189585B2Selective recess of interconnects for probing hybrid bond devicesINTEL CORP·Filed 2019·Granted Nov 30, 2021·3 cites·17 claims
- 4281US11901347B2Microelectronic package with three-dimensional (3D) monolithic memory dieINTEL CORP·Filed 2020·Granted Feb 13, 2024·1 cites·19 claims
- 4381US11171239B2Transistor channel passivation with 2D crystalline materialINTEL CORP·Filed 2019·Granted Nov 9, 2021·2 cites·17 claims
- 4481US6870270B2Method and structure for interfacing electronic devicesINTEL CORP·Filed 2002·Granted Mar 22, 2005·25 cites·26 claims
- 4580US12506059B2Vertically spaced intra-level interconnect line metallization for integrated circuit devicesINTEL CORP·Filed 2024·Granted Dec 23, 2025·0 cites·20 claims
- 4680US12278229B2Hybrid manufacturing for integrated circuit devices and assembliesINTEL CORP·Filed 2023·Granted Apr 15, 2025·0 cites·20 claims
- 4780US10720345B1Wafer to wafer bonding with low wafer distortionINTEL CORP·Filed 2018·Granted Jul 21, 2020·3 cites·13 claims
- 4880US8203208B2Three-dimensional stacked substrate arrangementsRAMANATHAN SHRIRAM·Filed 2011·Granted Jun 19, 2012·4 cites·7 claims
- 4980US2024389300A1Three-dimensional memory arrays with layer selector transistorsINTEL CORP·Filed 2024·Application pending·0 cites
- 5079US12230717B2Integrated circuit structures having partitioned source or drain contact structuresINTEL CORP·Filed 2023·Granted Feb 18, 2025·0 cites·21 claims
Showing the top 50 of 186 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →