Inventor · disambiguated record
Martin Langhammer
Also filed as: LANGHAMMER MARTIN
264 granted patents·61 pending applications·3,083 citations·filing 1998–2025
99Inventor score
Top patents by PatentIndex Score
325 records- 0198US7346644B1Devices and methods with programmable logic and digital signal processing regionsALTERA CORP·Filed 2006·Granted Mar 18, 2008·101 cites·4 claims
- 0298US6556044B2Programmable logic device including multipliers and configurations thereof to reduce resource utilizationALTERA CORP·Filed 2001·Granted Apr 29, 2003·233 cites·72 claims
- 0398US6538470B1Devices and methods with programmable logic and digital signal processing regionsALTERA CORP·Filed 2001·Granted Mar 25, 2003·318 cites·56 claims
- 0497US10922471B2High performance regularized network-on-chip architectureINTEL CORP·Filed 2019·Granted Feb 16, 2021·19 cites·20 claims
- 0597US9189200B1Multiple-precision processing block in a programmable integrated circuit deviceALTERA CORP·Filed 2013·Granted Nov 17, 2015·49 cites·31 claims
- 0697US7865541B1Configuring floating point operations in a programmable logic deviceALTERA CORP·Filed 2007·Granted Jan 4, 2011·69 cites·34 claims
- 0797US6781408B1Programmable logic device with routing channelsALTERA CORP·Filed 2002·Granted Aug 24, 2004·109 cites·37 claims
- 0896US9207908B1Digital signal processing blocks with embedded arithmetic circuitsALTERA CORP·Filed 2013·Granted Dec 8, 2015·33 cites·27 claims
- 0996US9098332B1Specialized processing block with fixed- and floating-point structuresLANGHAMMER MARTIN·Filed 2012·Granted Aug 4, 2015·45 cites·19 claims
- 1096US7725738B1FPGA configuration bitstream protection using multiple keysALTERA CORP·Filed 2005·Granted May 25, 2010·52 cites·19 claims
- 1196US7606362B1FPGA configuration bitstream encryption using modified keyALTERA CORP·Filed 2005·Granted Oct 20, 2009·40 cites·20 claims
- 1296US7590676B1Programmable logic device with specialized multiplier blocksALTERA CORP·Filed 2005·Granted Sep 15, 2009·60 cites·26 claims
- 1396US6628140B2Programmable logic devices with function-specific blocksALTERA CORP·Filed 2001·Granted Sep 30, 2003·108 cites·46 claims
- 1495US10042607B2Variable precision floating-point multiplierALTERA CORP·Filed 2016·Granted Aug 7, 2018·10 cites·17 claims
- 1595US9507565B1Programmable device implementing fixed and floating point functionality in a mixed architectureALTERA CORP·Filed 2014·Granted Nov 29, 2016·23 cites·21 claims
- 1695US9348557B1Fused floating point datapath with correct roundingALTERA CORP·Filed 2014·Granted May 24, 2016·24 cites·20 claims
- 1795US9235540B1Flexible high speed forward error correction (FEC) physical medium attachment (PMA) and physical coding sublayer (PCS) connection systemALTERA CORP·Filed 2013·Granted Jan 12, 2016·34 cites·18 claims
- 1895US8751551B2Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitryALTERA CORP·Filed 2013·Granted Jun 10, 2014·32 cites·10 claims
- 1995US8626815B1Configuring a programmable integrated circuit device to perform matrix multiplicationLANGHAMMER MARTIN·Filed 2009·Granted Jan 7, 2014·48 cites·25 claims
- 2095US7930336B2Large multiplier for programmable logic deviceALTERA CORP·Filed 2006·Granted Apr 19, 2011·47 cites·24 claims
- 2195US7822799B1Adder-rounder circuitry for specialized processing block in programmable logic deviceALTERA CORP·Filed 2006·Granted Oct 26, 2010·51 cites·29 claims
- 2294US9954553B1Circuitry and methods for continuous parallel decoder operationALTERA CORP·Filed 2015·Granted Apr 24, 2018·12 cites·18 claims
- 2394US9600278B1Programmable device using fixed and configurable logic to implement recursive treesALTERA CORP·Filed 2013·Granted Mar 21, 2017·24 cites·24 claims
- 2494US8788562B2Large multiplier for programmable logic deviceLANGHAMMER MARTIN·Filed 2011·Granted Jul 22, 2014·26 cites·20 claims
- 2594US8041759B1Specialized processing block for programmable logic deviceALTERA CORP·Filed 2006·Granted Oct 18, 2011·35 cites·27 claims
- 2693US9552189B1Embedded floating-point operator circuitryALTERA CORP·Filed 2014·Granted Jan 24, 2017·22 cites·36 claims
- 2793US8706790B1Implementing mixed-precision floating-point operations in a programmable integrated circuit deviceLANGHAMMER MARTIN·Filed 2009·Granted Apr 22, 2014·33 cites·18 claims
- 2893US8347192B1Parallel finite field vector operatorsALTERA CORP·Filed 2010·Granted Jan 1, 2013·19 cites·18 claims
- 2993US7818584B1One-time programmable memories for key storageALTERA CORP·Filed 2005·Granted Oct 19, 2010·29 cites·14 claims
- 3093US7230451B1Programmable logic device with routing channelsALTERA CORP·Filed 2005·Granted Jun 12, 2007·27 cites·19 claims
- 3192US8577951B1Matrix operations in an integrated circuit deviceLANGHAMMER MARTIN·Filed 2010·Granted Nov 5, 2013·18 cites·21 claims
- 3292US7734043B1Encryption key obfuscation and storageALTERA CORP·Filed 2005·Granted Jun 8, 2010·31 cites·19 claims
- 3392US6771094B1Devices and methods with programmable logic and digital signal processing regionsALTERA CORP·Filed 2003·Granted Aug 3, 2004·67 cites·20 claims
- 3491US8949298B1Computing floating-point polynomials in an integrated circuit deviceLANGHAMMER MARTIN·Filed 2011·Granted Feb 3, 2015·17 cites·26 claims
- 3591US8681974B1Array encryption coreLANGHAMMER MARTIN·Filed 2011·Granted Mar 25, 2014·13 cites·24 claims
- 3691US7836117B1Specialized processing block for programmable logic deviceALTERA CORP·Filed 2006·Granted Nov 16, 2010·31 cites·23 claims
- 3791US7216139B2Programmable logic device including multipliers and configurations thereof to reduce resource utilizationALTERA CORP·Filed 2005·Granted May 8, 2007·15 cites·18 claims
- 3891US6978287B1DSP processor architecture with write datapath word conditioning and analysisALTERA CORP·Filed 2001·Granted Dec 20, 2005·61 cites·34 claims
- 3990US10031846B1Transposition of two-dimensional arrays using single-bufferingALTERA CORP·Filed 2016·Granted Jul 24, 2018·9 cites·20 claims
- 4090US9331714B1Circuit structure and method for high-speed forward error correctionALTERA CORP·Filed 2013·Granted May 3, 2016·12 cites·21 claims
- 4190US8645449B1Combined floating point adder and subtractorLANGHAMMER MARTIN·Filed 2009·Granted Feb 4, 2014·23 cites·28 claims
- 4290US8300805B1AES core with independent inputs and outputsLANGHAMMER MARTIN·Filed 2007·Granted Oct 30, 2012·22 cites·39 claims
- 4390US8301681B1Specialized processing block for programmable logic deviceLEE KWAN YEE MARTIN·Filed 2006·Granted Oct 30, 2012·36 cites·11 claims
- 4490US7948267B1Efficient rounding circuits and methods in configurable integrated circuit devicesALTERA CORP·Filed 2010·Granted May 24, 2011·15 cites·24 claims
- 4590US6693455B2Programmable logic device including multipliers and configurations thereof to reduce resource utilizationALTERA CORPORATIONS·Filed 2003·Granted Feb 17, 2004·39 cites·10 claims
- 4689US9613232B1Digital signal processing blocks with embedded arithmetic circuitsALTERA CORP·Filed 2015·Granted Apr 4, 2017·5 cites·20 claims
- 4789US9348795B1Programmable device using fixed and configurable logic to implement floating-point roundingALTERA CORP·Filed 2013·Granted May 24, 2016·12 cites·15 claims
- 4889US8363833B1FPGA configuration bitstream encryption using modified keyALTERA CORP·Filed 2011·Granted Jan 29, 2013·8 cites·23 claims
- 4988US10732932B2Methods for using a multiplier circuit to support multiple sub-multiplications using bit correction and extensionINTEL CORP·Filed 2018·Granted Aug 4, 2020·6 cites·22 claims
- 5088US8996600B1Specialized processing block for implementing floating-point multiplier with subnormal operation supportLANGHAMMER MARTIN·Filed 2012·Granted Mar 31, 2015·11 cites·19 claims
Showing the top 50 of 325 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →