Inventor · disambiguated record
Manuel Mejia
Also filed as: MEJIA MANUEL · MEJIA MANUEL M
21 granted patents·1 pending application·1,173 citations·filing 1997–2003
97Inventor score
Files withALTERA CORP21
Top patents by PatentIndex Score
22 records- 0199US6215326B1Programmable logic device architecture with super-regions having logic regions and a memory regionALTERA CORP·Filed 1999·Granted Apr 10, 2001·331 cites·20 claims
- 0296US6344755B1Programmable logic device with redundant circuitryALTERA CORP·Filed 2000·Granted Feb 5, 2002·73 cites·15 claims
- 0396US6107824ACircuitry and methods for internal interconnection of programmable logic devicesALTERA CORP·Filed 1998·Granted Aug 22, 2000·103 cites·158 claims
- 0495US6052327ADual-port programmable logic device variable depth and width memory arrayALTERA CORP·Filed 1998·Granted Apr 18, 2000·110 cites·25 claims
- 0593US6417694B1Programmable logic device with hierarchical interconnection resourcesALTERA CORP·Filed 2001·Granted Jul 9, 2002·40 cites·9 claims
- 0693US5977793AProgrammable logic device with hierarchical interconnection resourcesALTERA CORP·Filed 1997·Granted Nov 2, 1999·87 cites·43 claims
- 0792US6201404B1Programmable logic device with redundant circuitryALTERA CORP·Filed 1999·Granted Mar 13, 2001·74 cites·33 claims
- 0892US6191998B1Programmable logic device memory array circuit having combinable single-port memory arraysALTERA CORP·Filed 1999·Granted Feb 20, 2001·104 cites·12 claims
- 0992US5883526AHierarchical interconnect for programmable logic devicesALTERA CORP·Filed 1997·Granted Mar 16, 1999·85 cites·20 claims
- 1086US6300794B1Programmable logic device with hierarchical interconnection resourcesALTERA CORP·Filed 2000·Granted Oct 9, 2001·23 cites·20 claims
- 1185US6577160B2Programmable logic device with hierarchical interconnection resourcesALTERA CORP·Filed 2002·Granted Jun 10, 2003·21 cites·12 claims
- 1279US6040712AApparatus and method for protecting a circuit during a hot socket conditionALTERA CORP·Filed 1999·Granted Mar 21, 2000·33 cites·20 claims
- 1369US6288970B1Programmable logic device memory array circuit having combinable single-port memory arraysALTERA CORP·Filed 1998·Granted Sep 11, 2001·28 cites·59 claims
- 1465US6335634B1Circuitry and methods for internal interconnection of programmable logic devicesFiled 2000·Granted Jan 1, 2002·10 cites·47 claims
- 1560US6798242B2Programmable logic device with hierarchical interconnection resourcesALTERA CORP·Filed 2003·Granted Sep 28, 2004·6 cites·4 claims
- 1657US6480028B2Programmable logic device architectures with super-regions having logic regions and memory regionALTERA CORP·Filed 2002·Granted Nov 12, 2002·5 cites·19 claims
- 1750US5872529ADynamic datastream compression/decompressionALTERA CORP·Filed 1997·Granted Feb 16, 1999·18 cites·17 claims
- 1848US6094064AProgrammable logic device incorporating and input/output overflow busALTERA CORP·Filed 1998·Granted Jul 25, 2000·9 cites·22 claims
- 1946US6879183B2Programmable logic device architectures with super-regions having logic regions and a memory regionALTERA CORP·Filed 2002·Granted Apr 12, 2005·2 cites·4 claims
- 2044US6392954B2Dual port programmable logic device variable depth and width memory arrayALTERA CORP·Filed 2000·Granted May 21, 2002·3 cites·22 claims
- 2143US6172900B1Compact, low voltage, noise-immune RAM cellALTERA CORP·Filed 1998·Granted Jan 9, 2001·8 cites·27 claims
- 2236US2001006348A1Programmable logic device architecturesALTERA CORP·Filed 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →