Inventor · disambiguated record
Maria L. Melo
Also filed as: MELO MARIA L · MELO MARIA LUCIA
20 granted patents·1,364 citations·filing 1989–1998
97Inventor score
Files withCOMPAQ COMPUTER CORP19
Top patents by PatentIndex Score
20 records- 0192US6212590B1Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion baseCOMPAQ COMPUTER CORP·Filed 1998·Granted Apr 3, 2001·198 cites·13 claims
- 0287US6199131B1Computer system employing optimized delayed transaction arbitration techniqueCOMPAQ COMPUTER CORP·Filed 1997·Granted Mar 6, 2001·141 cites·29 claims
- 0386US5987555ADynamic delayed transaction discard counter in a bus bridge of a computer systemCOMPAQ COMPUTER CORP·Filed 1997·Granted Nov 16, 1999·126 cites·27 claims
- 0485US5553248ASystem for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signalCOMPAQ COMPUTER CORP·Filed 1992·Granted Sep 3, 1996·111 cites·3 claims
- 0581US5819087AFlash ROM sharing between processor and microcontroller during booting and handling warm-booting eventsCOMPAQ COMPUTER CORP·Filed 1996·Granted Oct 6, 1998·87 cites·34 claims
- 0679US6279087B1System and method for maintaining coherency and improving performance in a bus bridge supporting write posting operationsCOMPAQ COMPUTER CORP·Filed 1997·Granted Aug 21, 2001·85 cites·25 claims
- 0779US6040845ADevice and method for reducing power consumption within an accelerated graphics port targetCOMPAQ COMPUTER CORP·Filed 1997·Granted Mar 21, 2000·70 cites·17 claims
- 0878US5471590ABus master arbitration circuitry having improved prioritizationCOMPAQ COMPUTER CORP·Filed 1994·Granted Nov 28, 1995·78 cites·9 claims
- 0977US6154838AFlash ROM sharing between processor and microcontroller during booting and handling warm-booting eventsFiled 1998·Granted Nov 28, 2000·69 cites·44 claims
- 1072US5991833AComputer system with bridge logic that reduces interference to CPU cycles during secondary bus transactionsCOMPAQ COMPUTER CORP·Filed 1998·Granted Nov 23, 1999·66 cites·25 claims
- 1172US5553310ASplit transactions and pipelined arbitration of microprocessors in multiprocessing computer systemsCOMPAQ COMPUTER CORP·Filed 1992·Granted Sep 3, 1996·64 cites·9 claims
- 1268US6243817B1Device and method for dynamically reducing power consumption within input buffers of a bus interface unitCOMPAQ COMPUTER CORP·Filed 1997·Granted Jun 5, 2001·55 cites·15 claims
- 1366US5923859ADual arbiters for arbitrating access to a first and second bus in a computer system having bus masters on each busCOMPAQ COMPUTER CORP·Filed 1997·Granted Jul 13, 1999·50 cites·32 claims
- 1461US6241400B1Configuration logic within a PCI compliant bus interface unit which can be selectively disconnected from a clocking source to conserve powerCOMPAQ COMPUTER CORP·Filed 1997·Granted Jun 5, 2001·31 cites·14 claims
- 1557US5138706APassword protected enhancement configuration register for addressing an increased number of adapter circuit boards with target machine emulation capabilitiesCOMPAQ COMPUTER CORP·Filed 1989·Granted Aug 11, 1992·25 cites·17 claims
- 1656US5797020ABus master arbitration circuitry having improved prioritizationCOMPAQ COMPUTER CORP·Filed 1996·Granted Aug 18, 1998·31 cites·15 claims
- 1755US5918026APCI to PCI bridge for transparently completing transactions between agents on opposite sides of the bridgeCOMPAQ COMPUTER CORP·Filed 1996·Granted Jun 29, 1999·29 cites·55 claims
- 1847US5867728APreventing corruption in a multiple processor computer system during a peripheral device configuration cycleCOMPAQ COMPUTER CORP·Filed 1996·Granted Feb 2, 1999·20 cites·22 claims
- 1945US5625824ACircuit for selectively preventing a microprocessor from posting write cyclesCOMPAQ COMPUTER CORP·Filed 1995·Granted Apr 29, 1997·17 cites·18 claims
- 2039US5790869ACircuit for selectively preventing a microprocessor from posting write cyclesCOMPAQ COMPUTER CORP·Filed 1997·Granted Aug 4, 1998·11 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →