Inventor · disambiguated record
Mahalingam Nagarajan
Also filed as: NAGARAJAN MAHALINGAM
11 granted patents·1 pending application·105 citations·filing 2005–2023
87Inventor score
Top patents by PatentIndex Score
12 records- 0195US7570704B2Transmitter architecture for high-speed communicationsINTEL CORP·Filed 2005·Granted Aug 4, 2009·78 cites·21 claims
- 0288US11551730B2Low power memory system using dual input-output voltage suppliesQUALCOMM INC·Filed 2021·Granted Jan 10, 2023·2 cites·30 claims
- 0388US11120863B2System and method for compensating for SDRAM signal timing drift through periodic write trainingQUALCOMM INC·Filed 2020·Granted Sep 14, 2021·3 cites·30 claims
- 0481US11662765B1System for providing a low latency and fast switched cascaded dual phased lock loop (PLL) architecture for die-to-die / system-on-chip (SoC) interfacesQUALCOMM INC·Filed 2022·Granted May 30, 2023·1 cites·30 claims
- 0581US8542046B2Apparatus, system, and method for voltage swing and duty cycle adjustmentROYTMAN EDUARD·Filed 2011·Granted Sep 24, 2013·6 cites·23 claims
- 0679US9319039B2Forwarded clock jitter reductionROYTMAN EDUARD·Filed 2011·Granted Apr 19, 2016·7 cites·15 claims
- 0774US7332947B2Method and apparatus for distorting duty cycle of a clockINTEL CORP·Filed 2005·Granted Feb 19, 2008·7 cites·8 claims
- 0873US11823762B2Low power memory system using dual input-output voltage suppliesQUALCOMM INC·Filed 2023·Granted Nov 21, 2023·0 cites·30 claims
- 0959US9966938B2Forwarded clock jitter reductionINTEL CORP·Filed 2016·Granted May 8, 2018·1 cites·26 claims
- 1055US11493949B2Clocking scheme to receive dataQUALCOMM INC·Filed 2020·Granted Nov 8, 2022·0 cites·20 claims
- 1152US2024038672A1Package comprising integrated devicesQUALCOMM INC·Filed 2022·Application pending·0 cites
- 1240US9160320B2Apparatus, system, and method for voltage swing and duty cycle adjustmentROYTMAN EDUARD·Filed 2013·Granted Oct 13, 2015·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →