Inventor · disambiguated record
Masahiko Nakamae
Also filed as: NAKAMAE MASAHIKO · TOKUYOSHI FUJIKI
9 granted patents·1 pending application·275 citations·filing 1977–2007
90Inventor score
Top patents by PatentIndex Score
10 records- 0188US4800177ASemiconductor device having multilayer silicide contact system and process of fabrication thereofNEC CORP·Filed 1986·Granted Jan 24, 1989·71 cites·4 claims
- 0285US5296391AMethod of manufacturing a bipolar transistor having thin base regionNEC CORP·Filed 1993·Granted Mar 22, 1994·64 cites·5 claims
- 0382US6091081AInsulating film comprising amorphous carbon fluoride, a semiconductor device comprising such an insulating filmNEC CORP·Filed 1997·Granted Jul 18, 2000·55 cites·13 claims
- 0476US7253082B2Pasted SOI substrate, process for producing the same and semiconductor deviceSUMITOMO MITSUBISHI SILICON·Filed 2003·Granted Aug 7, 2007·25 cites·10 claims
- 0569US6372628B1Insulating film comprising amorphous carbon fluoride, a semiconductor device comprising such an insulating film, and a method for manufacturing the semiconductor deviceNEC CORP·Filed 2000·Granted Apr 16, 2002·11 cites·3 claims
- 0668US7977221B2Method for producing strained Si-SOI substrate and strained Si-SOI substrate produced by the sameSUMCO CORP·Filed 2007·Granted Jul 12, 2011·4 cites·9 claims
- 0765US7767548B2Method for manufacturing semiconductor wafer including a strained silicon layerSUMCO CORP·Filed 2007·Granted Aug 3, 2010·4 cites·20 claims
- 0865US4963957ASemiconductor device having bipolar transistor with trenchNEC CORP·Filed 1988·Granted Oct 16, 1990·33 cites·6 claims
- 0940US4191595AMethod of manufacturing PN junctions in a semiconductor region to reach an isolation layer without exposing the semiconductor region surfaceNIPPON ELECTRIC CO·Filed 1977·Granted Mar 4, 1980·8 cites·6 claims
- 1039US2006214257A1Production method of strained silicon-SOI substrate and strained silicon-SOI substrate produced by sameNAT UNIVERSITY CORP·Filed 2006·Application pending·0 cites
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