Inventor · disambiguated record
Matteo Patelmo
Also filed as: PATELMO MATTEO
25 granted patents·2 pending applications·283 citations·filing 1999–2022
96Inventor score
Files withST MICROELECTRONICS SRL26
Top patents by PatentIndex Score
27 records- 0189US6350652B1Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regionsST MICROELECTRONICS SRL·Filed 2000·Granted Feb 26, 2002·55 cites·16 claims
- 0277US6528885B2Anti-deciphering contactsST MICROELECTRONICS SRL·Filed 2001·Granted Mar 4, 2003·24 cites·28 claims
- 0375US6624015B2Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctionsST MICROELECTRONICS SRL·Filed 2001·Granted Sep 23, 2003·17 cites·12 claims
- 0474US6281077B1Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctionsST MICROELECTRONICS SRL·Filed 1999·Granted Aug 28, 2001·27 cites·13 claims
- 0570US6521957B2Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cellST MICROELECTRONICS SRL·Filed 2000·Granted Feb 18, 2003·10 cites·7 claims
- 0670US6420769B2Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctionsST MICROELECTRONICS SRL·Filed 2001·Granted Jul 16, 2002·13 cites·12 claims
- 0768US6278159B1Process for the manufacture of integrated devices with gate oxide protection from manufacturing process damage, and protection structure thereforST MICROELECTRONICS SRL·Filed 1999·Granted Aug 21, 2001·24 cites·15 claims
- 0862US6614080B2Mask programmed ROM inviolable by reverse engineering inspections and method of fabricationST MICROELECTRONICS SRL·Filed 2001·Granted Sep 2, 2003·11 cites·25 claims
- 0962US6251728B1Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctionsST MICROELECTRONICS SRL·Filed 1999·Granted Jun 26, 2001·17 cites·12 claims
- 1060US6573130B1Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistorsST MICROELECTRONICS SRL·Filed 1999·Granted Jun 3, 2003·17 cites·11 claims
- 1160US6351008B1Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctionsST MICROELECTRONICS SRL·Filed 1999·Granted Feb 26, 2002·17 cites·8 claims
- 1259US6501147B1Process for manufacturing electronic devices comprising high voltage MOS transistors, and electronic device thus obtainedST MICROELECTRONICS SRL·Filed 2000·Granted Dec 31, 2002·8 cites·9 claims
- 1355US6274411B1Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masksST MICROELECTRONICS SRL·Filed 1999·Granted Aug 14, 2001·14 cites·19 claims
- 1447US2022384585A1Integrated electronic circuit including a field plate for the local reduction of the electric field and related manufacturing processST MICROELECTRONICS SRL·Filed 2022·Application pending·0 cites
- 1545US6551892B2Process for the manufacture of integrated devices with gate oxide protection from manufacturing process damage, and protection structure thereforST MICROELECTRONICS SRL·Filed 2001·Granted Apr 22, 2003·2 cites·2 claims
- 1645US6396101B2Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctionsST MICROELECTRONICS SRL·Filed 2001·Granted May 28, 2002·2 cites·7 claims
- 1744US6414349B1High efficiency memory deviceST MICROELECTRONICS SRL·Filed 2000·Granted Jul 2, 2002·2 cites·18 claims
- 1844US6340828B1Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regionsST MICROELECTRONICS SRL·Filed 2000·Granted Jan 22, 2002·2 cites·20 claims
- 1943US6576517B1Method for obtaining a multi-level ROM in an EEPROM process flowST MICROELECTRONICS SRL·Filed 1999·Granted Jun 10, 2003·8 cites·10 claims
- 2041US6240011B1Eeprom cell with improved current performanceST MICROELECTRONICS SRL·Filed 2000·Granted May 29, 2001·1 cites·11 claims
- 2139US6177313B1Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cellST MICROELECTRONICS SRL·Filed 1999·Granted Jan 23, 2001·4 cites·9 claims
- 2237US6300181B1Process for manufacturing an electronic device including MOS transistors with salicided junctions and non-salicided resistorsST MICROELECTRONICS SRL·Filed 1999·Granted Oct 9, 2001·5 cites·15 claims
- 2334US6284607B1Method of making high-voltage HV transistors with drain extension in a CMOS process of the dual gate type with silicideST MICROELECTRONICS SRL·Filed 1999·Granted Sep 4, 2001·3 cites·13 claims
- 2433US2001022380A1Integrated MOS transistor with a high threshold voltage and low multiplication coefficientFiled 2000·Application pending·0 cites
- 2532US6677206B2Non-volatile high-performance memory device and relative manufacturing processST MICROELECTRONICS SRL·Filed 2000·Granted Jan 13, 2004·0 cites·8 claims
- 2630US6444526B1Simplified process for defining the tunnel area in non-aligned, non-volatile semiconductor memory cellsST MICROELECTRONICS SRL·Filed 1999·Granted Sep 3, 2002·0 cites·8 claims
- 2724US7072239B2Method and circuit for locating anomalous memory cellsST MICROELECTRONICS SRL·Filed 2004·Granted Jul 4, 2006·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →