Inventor · disambiguated record
Mark Pearce
Also filed as: PEARCE MARK · PEARCE MARK H
13 granted patents·1 pending application·74 citations·filing 2001–2022
91Inventor score
Top patents by PatentIndex Score
14 records- 0191US10585825B2Procedures for implementing source based routing within an interconnect fabric on a system on chipPROVINO TECH INC·Filed 2019·Granted Mar 10, 2020·8 cites·22 claims
- 0284US11003604B2Procedures for improving efficiency of an interconnect fabric on a system on chipPROVINO TECH INC·Filed 2019·Granted May 11, 2021·3 cites·27 claims
- 0383US10853282B2Arbitrating portions of transactions over virtual channels associated with an interconnectPROVINO TECH INC·Filed 2019·Granted Dec 1, 2020·3 cites·25 claims
- 0483US10838891B2Arbitrating portions of transactions over virtual channels associated with an interconnectPROVINO TECH INC·Filed 2019·Granted Nov 17, 2020·3 cites·48 claims
- 0581US11640362B2Procedures for improving efficiency of an interconnect fabric on a system on chipGOOGLE LLC·Filed 2021·Granted May 2, 2023·1 cites·20 claims
- 0681US11340671B2Protocol level control for system on a chip (SOC) agent reset and power managementGOOGLE LLC·Filed 2019·Granted May 24, 2022·2 cites·16 claims
- 0778US6816932B2Bus precharge during a phase of a clock signal to eliminate idle clock cycleBROADCOM CORP·Filed 2001·Granted Nov 9, 2004·23 cites·21 claims
- 0869US11914440B2Protocol level control for system on a chip (SoC) agent reset and power managementGOOGLE LLC·Filed 2022·Granted Feb 27, 2024·0 cites·20 claims
- 0966US6877085B2Mechanism for processing speclative LL and SC instructions in a pipelined processorBROADCOM CORP·Filed 2002·Granted Apr 5, 2005·10 cites·19 claims
- 1066US2022291730A1Protocol Level Control for System on a Chip (SOC) Agent Reset and Power ManagementGOOGLE LLC·Filed 2022·Application pending·0 cites
- 1163US7162613B2Mechanism for processing speculative LL and SC instructions in a pipelined processorBROADCOM CORP·Filed 2005·Granted Jan 9, 2007·2 cites·5 claims
- 1262US6646899B2Content addressable memory with power reduction techniqueBROADCOM CORP·Filed 2001·Granted Nov 11, 2003·11 cites·30 claims
- 1352US7076582B2Bus precharge during a phase of a clock signal to eliminate idle clock cycleBROADCOM CORP·Filed 2004·Granted Jul 11, 2006·2 cites·15 claims
- 1451US6785152B2Content addressable memory with power reduction techniqueBROADCOM CORP·Filed 2003·Granted Aug 31, 2004·6 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →