Inventor · disambiguated record
Marion G. Porter
Also filed as: NORMAN ROBERT W JR · PORTER MARION G
22 granted patents·967 citations·filing 1975–1988
97Inventor score
Top patents by PatentIndex Score
22 records- 0192US4110822AInstruction look ahead having prefetch concurrency and pipeline featuresHONEYWELL INF SYSTEMS·Filed 1977·Granted Aug 29, 1978·89 cites·7 claims
- 0287US4099234AInput/output processing system utilizing locked processorsHONEYWELL INF SYSTEMS·Filed 1976·Granted Jul 4, 1978·80 cites·41 claims
- 0387US4010450AFail soft memoryHONEYWELL INF SYSTEMS·Filed 1975·Granted Mar 1, 1977·34 cites·15 claims
- 0485US4268907ACache unit bypass apparatusHONEYWELL INF SYSTEMS·Filed 1979·Granted May 19, 1981·54 cites·38 claims
- 0582US4530052AApparatus and method for a data processing unit sharing a plurality of operating systemsHONEYWELL INF SYSTEMS·Filed 1982·Granted Jul 16, 1985·67 cites·6 claims
- 0681US4091455AInput/output maintenance access apparatusHONEYWELL INF SYSTEMS·Filed 1976·Granted May 23, 1978·50 cites·30 claims
- 0780US4471429AApparatus for cache clearingHONEYWELL INF SYSTEMS·Filed 1982·Granted Sep 11, 1984·55 cites·6 claims
- 0879US4225922ACommand queue apparatus included within a cache unit for facilitating command sequencingHONEYWELL INF SYSTEMS·Filed 1978·Granted Sep 30, 1980·40 cites·41 claims
- 0978US4525777ASplit-cycle cache system with SCU controlled cache clearing during cache store access periodHONEYWELL INF SYSTEMS·Filed 1981·Granted Jun 25, 1985·58 cites·9 claims
- 1078US4493034AApparatus and method for an operating system supervisor in a data processing systemHONEYWELL INF SYSTEMS·Filed 1982·Granted Jan 8, 1985·55 cites·17 claims
- 1178US4124891AMemory access systemHONEYWELL INF SYSTEMS·Filed 1976·Granted Nov 7, 1978·45 cites·27 claims
- 1277US4314331ACache unit information replacement apparatusHONEYWELL INF SYSTEMS·Filed 1978·Granted Feb 2, 1982·38 cites·35 claims
- 1377US4208716ACache arrangement for performing simultaneous read/write operationsHONEYWELL INF SYSTEMS·Filed 1978·Granted Jun 17, 1980·38 cites·39 claims
- 1474US4245304ACache arrangement utilizing a split cycle mode of operationHONEYWELL INF SYSTEMS·Filed 1978·Granted Jan 13, 1981·33 cites·39 claims
- 1573US4313158ACache apparatus for enabling overlap of instruction fetch operationsHONEYWELL INF SYSTEMS·Filed 1978·Granted Jan 26, 1982·32 cites·34 claims
- 1673US4217640ACache unit with transit block buffer apparatusHONEYWELL INF SYSTEMS·Filed 1978·Granted Aug 12, 1980·31 cites·37 claims
- 1769US3976978AMethod of generating addresses to a paged memoryHONEYWELL INF SYSTEMS·Filed 1975·Granted Aug 24, 1976·27 cites·13 claims
- 1868US3976977AProcessor for input-output processing systemHONEYWELL INF SYSTEMS·Filed 1975·Granted Aug 24, 1976·31 cites·8 claims
- 1966US4933941AApparatus and method for testing the operation of a central processing unit of a data processing systemHONEYWELL BULL·Filed 1988·Granted Jun 12, 1990·39 cites·18 claims
- 2063US4312036AInstruction buffer apparatus of a cache unitHONEYWELL INF SYSTEMS·Filed 1978·Granted Jan 19, 1982·23 cites·39 claims
- 2161US4001788APathfinder microprogram control systemHONEYWELL INF SYSTEMS·Filed 1975·Granted Jan 4, 1977·22 cites·20 claims
- 2259US4831622AApparatus for forcing a reload from main memory upon cache memory errorHONEYWELL BULL·Filed 1987·Granted May 16, 1989·26 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →