Inventor · disambiguated record
Mark S. Rodder
Also filed as: RODDER MARK · RODDER MARK S · RODDER MARK STEPHEN
167 granted patents·14 pending applications·3,124 citations·filing 1988–2024
99Inventor score
Files withSAMSUNG ELECTRONICS CO LTD92TEXAS INSTRUMENTS INC63OBRADOVIC BORNA J5KITTL JORGE A3RODDER MARK S3
Top patents by PatentIndex Score
181 records- 0199US10008583B1Gate-all-around nanosheet field-effect transistors and methods of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Jun 26, 2018·78 cites·9 claims
- 0299US9570395B1Semiconductor device having buried power railSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Feb 14, 2017·94 cites·20 claims
- 0398US11088258B2Method of forming multiple-Vt FETs for CMOS circuit applicationsSAMSUNG ELECTRONICS CO LTD·Filed 2020·Granted Aug 10, 2021·6 cites·20 claims
- 0498US10026652B2Horizontal nanosheet FETs and method of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Jul 17, 2018·21 cites·13 claims
- 0598US9941405B2Nanosheet and nanowire devices having source/drain stressors and methods of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Apr 10, 2018·25 cites·15 claims
- 0698US9853114B1Field effect transistor with stacked nanowire-like channels and methods of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Dec 26, 2017·24 cites·20 claims
- 0798US9812449B2Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitanceSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Nov 7, 2017·30 cites·20 claims
- 0898US9711414B2Strained stacked nanosheet FETS and/or quantum well stacked nanosheetSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Jul 18, 2017·32 cites·30 claims
- 0998US9647098B2Thermionically-overdriven tunnel FETs and methods of fabricating the sameSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted May 9, 2017·42 cites·24 claims
- 1098US9490323B2Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective widthSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Nov 8, 2016·37 cites·18 claims
- 1198US9461114B2Semiconductor devices with structures for suppression of parasitic bipolar effect in stacked nanosheet FETs and methods of fabricating the sameOBRADOVIC BORNA J·Filed 2015·Granted Oct 4, 2016·43 cites·20 claims
- 1297US9601586B1Methods of forming semiconductor devices, including forming a metal layer on source/drain regionsSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Mar 21, 2017·18 cites·20 claims
- 1397US9570609B2Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the sameOBRADOVIC BORNA J·Filed 2015·Granted Feb 14, 2017·56 cites·20 claims
- 1497US9287357B2Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the sameSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Mar 15, 2016·66 cites·20 claims
- 1596US9466669B2Multiple channel length finFETs with same physical gate lengthSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Oct 11, 2016·16 cites·9 claims
- 1696US8828818B1Methods of fabricating integrated circuit device with fin transistors having different threshold voltagesSAMSUNG ELECTRONICS CO LTD·Filed 2013·Granted Sep 9, 2014·29 cites·11 claims
- 1796US6461928B2Methodology for high-performance, high reliability input/output devices and analog-compatible input/output and core devices using core device implantsTEXAS INSTRUMENTS INC·Filed 2001·Granted Oct 8, 2002·124 cites·15 claims
- 1895US11983622B2High-density neuromorphic computing elementSAMSUNG ELECTRONICS CO LTD·Filed 2023·Granted May 14, 2024·1 cites·15 claims
- 1995US11749739B2Method of forming multiple-Vt FETS for CMOS circuit applicationsSAMSUNG ELECTRONICS CO LTD·Filed 2021·Granted Sep 5, 2023·2 cites·20 claims
- 2095US9905672B2Method of forming internal dielectric spacers for horizontal nanosheet FET architecturesSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Feb 27, 2018·14 cites·19 claims
- 2195US9773886B1Nanosheet and nanowire devices having doped internal spacers and methods of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Sep 26, 2017·14 cites·20 claims
- 2295US9685564B2Gate-all-around field effect transistors with horizontal nanosheet conductive channel structures for MOL/inter-channel spacing and related cell architecturesSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Jun 20, 2017·13 cites·20 claims
- 2395US9064699B2Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methodsWANG WEI-E·Filed 2014·Granted Jun 23, 2015·30 cites·20 claims
- 2495US5079180AMethod of fabricating a raised source/drain transistorTEXAS INSTRUMENTS INC·Filed 1990·Granted Jan 7, 1992·132 cites·16 claims
- 2594US10811415B2Semiconductor device and method for making the sameSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Oct 20, 2020·10 cites·20 claims
- 2694US4998150ARaised source/drain transistorTEXAS INSTRUMENTS INC·Filed 1988·Granted Mar 5, 1991·104 cites·17 claims
- 2793US9653287B2S/D connection to individual channel layers in a nanosheet FETSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted May 16, 2017·11 cites·16 claims
- 2892US10566330B2Dielectric separation of partial GAA FETsSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Feb 18, 2020·10 cites·20 claims
- 2992US9960232B2Horizontal nanosheet FETs and methods of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted May 1, 2018·7 cites·13 claims
- 3092US9831323B2Structure and method to achieve compressively strained Si NSSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Nov 28, 2017·8 cites·20 claims
- 3192US9793403B2Multi-layer fin field effect transistor devices and methods of forming the sameOBRADOVIC BORNA J·Filed 2016·Granted Oct 17, 2017·9 cites·20 claims
- 3292US9263549B2Fin-FET transistor with punchthrough barrier and leakage protection regionsSAMSUNG ELECTRONICS CO LTD·Filed 2013·Granted Feb 16, 2016·15 cites·19 claims
- 3392US5087581AMethod of forming vertical FET device with low gate to source overlap capacitanceTEXAS INSTRUMENTS INC·Filed 1990·Granted Feb 11, 1992·83 cites·12 claims
- 3492US4877755AMethod of forming silicides having different thicknessesTEXAS INSTRUMENTS INC·Filed 1988·Granted Oct 31, 1989·71 cites·18 claims
- 3590US9343303B2Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devicesWANG WEI-E·Filed 2014·Granted May 17, 2016·11 cites·19 claims
- 3690US8927373B2Methods of fabricating non-planar transistors including current enhancing structuresSAMSUNG ELECTRONICS CO LTD·Filed 2013·Granted Jan 6, 2015·9 cites·20 claims
- 3790US6346447B1Shallow-implant elevated source/drain doping from a sidewall dopant sourceTEXAS INSTRUMENTS INC·Filed 1999·Granted Feb 12, 2002·74 cites·9 claims
- 3890US6083836ATransistors with substitutionally formed gate structures and methodTEXAS INSTRUMENTS INC·Filed 1998·Granted Jul 4, 2000·88 cites·20 claims
- 3990US6063675AMethod of forming a MOSFET using a disposable gate with a sidewall dielectricTEXAS INSTRUMENTS INC·Filed 1997·Granted May 16, 2000·85 cites·12 claims
- 4089US9899529B2Method to make self-aligned vertical field effect transistorSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Feb 20, 2018·5 cites·18 claims
- 4189US9768062B1Method for forming low parasitic capacitance source and drain contactsSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Sep 19, 2017·8 cites·20 claims
- 4289US9178045B2Integrated circuit devices including FinFETS and methods of forming the sameOBRADOVIC BORNA J·Filed 2014·Granted Nov 3, 2015·9 cites·22 claims
- 4389US6251761B1Process for polycrystalline silicon gates and high-K dielectric compatibilityTEXAS INSTRUMENTS INC·Filed 1999·Granted Jun 26, 2001·85 cites·19 claims
- 4489US5073519AMethod of fabricating a vertical FET device with low gate to drain overlap capacitanceTEXAS INSTRUMENTS INC·Filed 1990·Granted Dec 17, 1991·79 cites·5 claims
- 4588US9978833B2Methods for varied strain on nano-scale field effect transistor devicesSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted May 22, 2018·5 cites·18 claims
- 4688US9870940B2Methods of forming nanosheets on lattice mismatched substratesSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Jan 16, 2018·5 cites·20 claims
- 4787US10910313B2Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitchSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Feb 2, 2021·5 cites·12 claims
- 4887US6127233ALateral MOSFET having a barrier between the source/drain regions and the channel regionTEXAS INSTRUMENTS INC·Filed 1998·Granted Oct 3, 2000·59 cites·2 claims
- 4987US6124627ALateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain regionTEXAS INSTRUMENTS INC·Filed 1999·Granted Sep 26, 2000·72 cites·4 claims
- 5087US6063677AMethod of forming a MOSFET using a disposable gate and raised source and drainTEXAS INSTRUMENTS INC·Filed 1997·Granted May 16, 2000·91 cites·32 claims
Showing the top 50 of 181 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →