Inventor · disambiguated record
Marek Syrzycki
Also filed as: SYRZYCKI MAREK
3 granted patents·75 citations·filing 1997–1999
73Inventor score
Top patents by PatentIndex Score
3 records- 0177US5910874AGate-coupled structure for enhanced ESD input/output pad protection in CMOS ICsPMC SIERRA LTD·Filed 1997·Granted Jun 8, 1999·56 cites·7 claims
- 0247US5989931ALow-cost methods for manufacturing field ionization and emission structures with self-aligned gate electrodesUNIV FRASER SIMON·Filed 1997·Granted Nov 23, 1999·12 cites·26 claims
- 0337US6128171AGate-coupled structure for enhanced ESD input/output pad protection in CMOS ICsPMC SIERRA LTD·Filed 1999·Granted Oct 3, 2000·7 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →