Inventor · disambiguated record
Mark E. Thierbach
Also filed as: THIERBACH MARK · THIERBACH MARK E · THIERBACH MARK ERNEST
16 granted patents·255 citations·filing 1981–2008
94Inventor score
Files withLUCENT TECHNOLOGIES INC6AGERE SYSTEMS INC3AT & T CORP3AGERE SYST GUARDIAN CORP1AMERICAN TELEPHONE & TELEGRAPH1
Top patents by PatentIndex Score
16 records- 0178US4661922AProgrammed logic array with two-level control timingAMERICAN TELEPHONE & TELEGRAPH·Filed 1982·Granted Apr 28, 1987·22 cites·6 claims
- 0270US5432804ADigital processor and viterbi decoder having shared memoryAT & T CORP·Filed 1993·Granted Jul 11, 1995·32 cites·9 claims
- 0355US6530014B2Near-orthogonal dual-MAC instruction set architecture with minimal encoding bitsAGERE SYSTEMS INC·Filed 1998·Granted Mar 4, 2003·30 cites·14 claims
- 0453US5454014ADigital signal processorAT & T CORP·Filed 1993·Granted Sep 26, 1995·15 cites·5 claims
- 0552US5559837AEfficient utilization of present state/next state registersLUCENT TECHNOLOGIES INC·Filed 1995·Granted Sep 24, 1996·14 cites·11 claims
- 0649US5802382AFlexible single chip digital processor architectureLUCENT TECHNOLOGIES INC·Filed 1995·Granted Sep 1, 1998·21 cites·24 claims
- 0747US5465275AEfficient utilization of present state/next state registersAT & T CORP·Filed 1993·Granted Nov 7, 1995·11 cites·3 claims
- 0845US6073228AModulo address generator for generating an updated addressLUCENT TECHNOLOGIES INC·Filed 1997·Granted Jun 6, 2000·22 cites·15 claims
- 0945US4399516AStored-program control machineBELL TELEPHONE LABOR INC·Filed 1981·Granted Aug 16, 1983·14 cites·10 claims
- 1044US4493029AMicroprocessor with PLA adapted to implement subroutinesAT & T BELL LAB·Filed 1982·Granted Jan 8, 1985·13 cites·8 claims
- 1143US6467035B2System and method for performing table look-ups using a multiple data fetch architectureAGERE SYST GUARDIAN CORP·Filed 1997·Granted Oct 15, 2002·16 cites·13 claims
- 1242US6092179ACore processor with customizable function unitLUCENT TECHNOLOGIES INC·Filed 1997·Granted Jul 18, 2000·13 cites·52 claims
- 1341US6115805ANon-aligned double word fetch bufferLUCENT TECHNOLOGIES INC·Filed 1998·Granted Sep 5, 2000·15 cites·18 claims
- 1434US6801995B1Method for optimally encoding a set of instruction codes for a digital processor having a plurality of instruction selectable resource types and an associated optimized set of instruction codesAGERE SYSTEMS INC·Filed 1998·Granted Oct 5, 2004·8 cites·15 claims
- 1534US6148386AAddress generator circuity for a circular bufferLUCENT TECHNOLOGIES INC·Filed 1998·Granted Nov 14, 2000·9 cites·12 claims
- 1632US7818135B2Optimum timing of write and read clock pathsAGERE SYSTEMS INC·Filed 2008·Granted Oct 19, 2010·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →