Inventor · disambiguated record
Martin Versen
Also filed as: VERSEN MARTIN
17 granted patents·6 pending applications·65 citations·filing 2002–2008
91Inventor score
Files withINFINEON TECHNOLOGIES AG14QIMONDA AG3VERSEN MARTIN3INFINEON TECHNOLOGIES CORP1NIERLE KLAUS1
Top patents by PatentIndex Score
23 records- 0181US7263019B2Serial presence detect functionality on memory componentINFINEON TECHNOLOGIES AG·Filed 2005·Granted Aug 28, 2007·10 cites·23 claims
- 0268US7203106B2Integrated semiconductor memory with redundant memory cellsINFINEON TECHNOLOGIES AG·Filed 2005·Granted Apr 10, 2007·7 cites·25 claims
- 0367US7542362B2Sense-amplifier circuit for a memory device with an open bit line architectureQIMONDA AG·Filed 2007·Granted Jun 2, 2009·6 cites·25 claims
- 0459US7308624B2Voltage monitoring test mode and test adapterINFINEON TECHNOLOGIES CORP·Filed 2005·Granted Dec 11, 2007·4 cites·7 claims
- 0559US7257038B2Test mode for IPP current measurement for wordline defect detectionINFINEON TECHNOLOGIES AG·Filed 2006·Granted Aug 14, 2007·5 cites·23 claims
- 0658US7184337B2Method for testing an integrated semiconductor memoryINFINEON TECHNOLOGIES AG·Filed 2005·Granted Feb 27, 2007·4 cites·13 claims
- 0758US7124336B2Method for the defect analysis of memory modulesINFINEON TECHNOLOGIES AG·Filed 2002·Granted Oct 17, 2006·11 cites·11 claims
- 0849US7339841B2Test mode method and apparatus for internal memory timing signalsINFINEON TECHNOLOGIES AG·Filed 2005·Granted Mar 4, 2008·2 cites·25 claims
- 0948US7120070B2Method for testing the serviceability of bit lines in a DRAM memory deviceINFINEON TECHNOLOGIES AG·Filed 2004·Granted Oct 10, 2006·6 cites·12 claims
- 1048US6703844B2Method for determining the transit time of electrical signals on printed circuit boards using automatic standard test equipmentINFINEON TECHNOLOGIES AG·Filed 2002·Granted Mar 9, 2004·4 cites·5 claims
- 1145US7405986B2Redundant wordline deactivation schemeINFINEON TECHNOLOGIES AG·Filed 2005·Granted Jul 29, 2008·1 cites·32 claims
- 1245US7340313B2Monitoring device for monitoring internal signals during initialization of an electronic circuitINFINEON TECHNOLOGIES AG·Filed 2005·Granted Mar 4, 2008·1 cites·6 claims
- 1343US2004034809A1Memory management configuration and method for making a main memoryFiled 2003·Application pending·0 cites
- 1440US7729186B2Method and system for testing an integrated circuitQIMONDA AG·Filed 2008·Granted Jun 1, 2010·0 cites·19 claims
- 1540US2007038804A1Testmode and test method for increased stress duty cycles during burn inNIERLE KLAUS·Filed 2005·Application pending·0 cites
- 1639US6862234B2Method and test circuit for testing a dynamic memory circuitINFINEON TECHNOLOGIES AG·Filed 2004·Granted Mar 1, 2005·4 cites·20 claims
- 1736US2009021996A1Memory Circuit, Memory Component, Data Processing System and Method of Testing a Memory CircuitVERSEN MARTIN·Filed 2008·Application pending·0 cites
- 1834US7428673B2Test method for determining the wire configuration for circuit carriers with components arranged thereonINFINEON TECHNOLOGIES AG·Filed 2005·Granted Sep 23, 2008·0 cites·18 claims
- 1934US7191085B2Method for testing an electric circuitINFINEON TECHNOLOGIES AG·Filed 2005·Granted Mar 13, 2007·0 cites·20 claims
- 2034US2009295342A1Circuit and Method for Limiting a Current Flow in Case of a Shortage of a Support CapacitorVERSEN MARTIN·Filed 2008·Application pending·0 cites
- 2134US2007094554A1Chip specific test mode execution on a memory moduleVERSEN MARTIN·Filed 2005·Application pending·0 cites
- 2233US2007250745A1Method and system for testing a memory deviceQIMONDA AG·Filed 2007·Application pending·0 cites
- 2332US7380182B2Method and apparatus for checking output signals of an integrated circuitINFINEON TECHNOLOGIES AG·Filed 2004·Granted May 27, 2008·0 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →