Inventor · disambiguated record
Merwin H. Alferness
Also filed as: ALFERNESS MERWIN H · ALFERNESS MERWIN HERSCHER
19 granted patents·1 pending application·883 citations·filing 1991–2003
96Inventor score
Top patents by PatentIndex Score
20 records- 0192US6684376B1Method and apparatus for selecting components within a circuit design databaseUNISYS CORP·Filed 1997·Granted Jan 27, 2004·205 cites·28 claims
- 0281US6029205ASystem architecture for improved message passing and process synchronization between concurrently executing processesUNISYS CORP·Filed 1997·Granted Feb 22, 2000·121 cites·48 claims
- 0381US5701316AMethod for generating an internet protocol suite checksum in a single macro instructionUNISYS CORP·Filed 1995·Granted Dec 23, 1997·131 cites·21 claims
- 0479US6629236B1Master-slave latch circuit for multithreaded processingIBM·Filed 1999·Granted Sep 30, 2003·74 cites·17 claims
- 0571US6247064B1Enqueue instruction in a system architecture for improved message passing and process synchronizationUNISYS CORP·Filed 1994·Granted Jun 12, 2001·58 cites·22 claims
- 0670US5555396AHierarchical queuing in a system architecture for improved message passing and process synchronizationUNISYS CORP·Filed 1994·Granted Sep 10, 1996·55 cites·4 claims
- 0764US5896522ASelective emulation interpretation using transformed instructionsUNISYS CORP·Filed 1996·Granted Apr 20, 1999·45 cites·29 claims
- 0859US7130270B2Method and apparatus for varying bandwidth provided to virtual channels in a virtual pathIBM·Filed 2002·Granted Oct 31, 2006·5 cites·8 claims
- 0959US7069557B2Network processor which defines virtual paths without using logical path descriptorsIBM·Filed 2002·Granted Jun 27, 2006·5 cites·4 claims
- 1058US6278959B1Method and system for monitoring the performance of a data processing systemIBM·Filed 1999·Granted Aug 21, 2001·32 cites·46 claims
- 1154US5577259AInstruction processor control system using separate hardware and microcode control signals to control the pipelined execution of multiple classes of machine instructionsUNISYS CORP·Filed 1994·Granted Nov 19, 1996·30 cites·30 claims
- 1253US5602998ADequeue instruction in a system architecture for improved message passing and process synchronizationUNISYS CORP·Filed 1994·Granted Feb 11, 1997·25 cites·8 claims
- 1348US5966515AParallel emulation system and methodUNISYS CORP·Filed 1996·Granted Oct 12, 1999·20 cites·34 claims
- 1447US5611065AAddress prediction for relative-to-absolute addressingUNISYS CORP·Filed 1994·Granted Mar 11, 1997·20 cites·10 claims
- 1546US2003200424A1Master-slave latch circuit for multithreaded processingIBM·Filed 2003·Application pending·0 cites
- 1642US5363490AApparatus for and method of conditionally aborting an instruction within a pipelined architectureUNISYS CORP·Filed 1992·Granted Nov 8, 1994·14 cites·7 claims
- 1741US6754879B1Method and apparatus for providing modularity to a behavioral description of a circuit designUNISYS CORP·Filed 1997·Granted Jun 22, 2004·19 cites·9 claims
- 1841US5414821AMethod of and apparatus for rapidly loading addressing environment by checking and loading multiple registers using a specialized instructionUNISYS CORP·Filed 1991·Granted May 9, 1995·15 cites·4 claims
- 1936US8769164B2Methods and apparatus for allocating bandwidth for a network processorALFERNESS MERWIN H·Filed 2003·Granted Jul 1, 2014·0 cites·23 claims
- 2036US5379392AMethod of and apparatus for rapidly loading addressing registersUNISYS CORP·Filed 1991·Granted Jan 3, 1995·9 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →