Inventor · disambiguated record
Mehdi Zamanian
Also filed as: ZAMANIAN MEHDI
23 granted patents·1 pending application·651 citations·filing 1990–2008
97Inventor score
Top patents by PatentIndex Score
24 records- 0193US6194276B1Radiation hardened semiconductor memoryST MICROELECTRONICS INC·Filed 2000·Granted Feb 27, 2001·54 cites·6 claims
- 0287US5171700AField effect transistor structure and methodSGS THOMSON MICROELECTRONICS·Filed 1991·Granted Dec 15, 1992·66 cites·17 claims
- 0386US7688669B2Programmable SRAM source bias scheme for use with switchable SRAM power supply sets of voltagesST MICROELECTRONICS INC·Filed 2008·Granted Mar 30, 2010·18 cites·25 claims
- 0485US6759717B2CMOS integrated circuit device with LDD n-channel transistor and non-LDD p-channel transistorST MICROELECTRONICS INC·Filed 2001·Granted Jul 6, 2004·35 cites·16 claims
- 0584US5272371AElectrostatic discharge protection structureSGS THOMSON MICROELECTRONICS·Filed 1991·Granted Dec 21, 1993·64 cites·20 claims
- 0682US5116777AMethod for fabricating semiconductor devices by use of an N+ buried layer for complete isolationSGS THOMSON MICROELECTRONICS·Filed 1990·Granted May 26, 1992·72 cites·15 claims
- 0780US6111319AMethod of forming submicron contacts and vias in an integrated circuitST MICROELECTRONICS INC·Filed 1995·Granted Aug 29, 2000·51 cites·13 claims
- 0875US6903616B2Startup circuit and method for starting an oscillator after power-offST MICROELECTRONICS INC·Filed 2003·Granted Jun 7, 2005·13 cites·29 claims
- 0975US6033980AMethod of forming submicron contacts and vias in an integrated circuitST MICROELECTRONICS INC·Filed 1997·Granted Mar 7, 2000·40 cites·5 claims
- 1075US5521401AP-N junction in a vertical memory cell that creates a high resistance loadSGS THOMSON MICROELECTRONICS·Filed 1994·Granted May 28, 1996·33 cites·18 claims
- 1174US6091630ARadiation hardened semiconductor memoryST MICROELECTRONICS INC·Filed 1999·Granted Jul 18, 2000·26 cites·20 claims
- 1273US6295224B1Circuit and method of fabricating a memory cell for a static random access memoryST MICROELECTRONICS INC·Filed 1999·Granted Sep 25, 2001·28 cites·20 claims
- 1372US5847460ASubmicron contacts and vias in an integrated circuitST MICROELECTRONICS INC·Filed 1995·Granted Dec 8, 1998·36 cites·20 claims
- 1462US5633196AMethod of forming a barrier and landing pad structure in an integrated circuitSGS THOMSON MICROELECTRONICS·Filed 1994·Granted May 27, 1997·18 cites·18 claims
- 1561US6153458AMethod of forming a portion of a memory cellST MICROELECTRONICS INC·Filed 1995·Granted Nov 28, 2000·18 cites·20 claims
- 1659US7064534B2Regulator circuitry and methodST MICROELECTRONICS INC·Filed 2003·Granted Jun 20, 2006·11 cites·21 claims
- 1759US5544097ASRAM memory cell with reduced internal cell voltageSGS THOMSON MICROELECTRONICS·Filed 1995·Granted Aug 6, 1996·19 cites·24 claims
- 1854US6486649B1Built-in frequency test circuit for testing the frequency of the output of a frequency generating circuitST MICROELECTRONICS INC·Filed 2000·Granted Nov 26, 2002·5 cites·22 claims
- 1953US5793111ABarrier and landing pad structure in an integrated circuitSGS THOMSON MICROELECTRONICS·Filed 1996·Granted Aug 11, 1998·12 cites·8 claims
- 2048US6221709B1Method of fabricating a CMOS integrated circuit device with LDD N-channel transistor and non-LDD P-channel transistorST MICROELECTRONICS INC·Filed 1997·Granted Apr 24, 2001·10 cites·19 claims
- 2146US6180517B1Method of forming submicron contacts and vias in an integrated circuitST MICROELECTRONICS INC·Filed 1997·Granted Jan 30, 2001·11 cites·27 claims
- 2244US2006001039A1Method of forming buried channels and microfluidic devices having the sameST MICROELECTRONICS INC·Filed 2004·Application pending·0 cites
- 2343US6057699ABuilt-in frequency test circuit for testing the frequency of the output of a frequency generating circuitST MICROELECTRONICS INC·Filed 1997·Granted May 2, 2000·9 cites·20 claims
- 2440US6486007B2Method of fabricating a memory cell for a static random access memoryST MICROELECTRONICS INC·Filed 2001·Granted Nov 26, 2002·2 cites·24 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →