Inventor · disambiguated record
Mitchell A. Bauman
Also filed as: BAUMAN MITCHELL · BAUMAN MITCHELL A · BAUMAN MITCHELL ANTHONY
54 granted patents·2 pending applications·2,825 citations·filing 1984–2012
99Inventor score
Top patents by PatentIndex Score
56 records- 0196US6799252B1High-performance modular memory system with crossbar connectionsUNISYS CORP·Filed 2001·Granted Sep 28, 2004·126 cites·37 claims
- 0292US6594785B1System and method for fault handling and recovery in a multi-processing system having hardware resources shared between multiple partitionsUNISYS CORP·Filed 2000·Granted Jul 15, 2003·146 cites·33 claims
- 0390US7047322B1System and method for performing conflict resolution and flow control in a multiprocessor systemUNISYS CORP·Filed 2003·Granted May 16, 2006·98 cites·32 claims
- 0490US6480927B1High-performance modular memory system with crossbar connectionsUNISYS CORP·Filed 1997·Granted Nov 12, 2002·145 cites·8 claims
- 0589US6381715B1System and method for performing parallel initialization and testing of multiple memory banks and interfaces in a shared memory moduleUNISYS CORP·Filed 1998·Granted Apr 30, 2002·83 cites·27 claims
- 0688US5678026AMulti-processor data processing system with control for granting multiple storage locks in parallel and parallel lock priority and second level cache priority queuesUNISYS CORP·Filed 1995·Granted Oct 14, 1997·155 cites·16 claims
- 0787US5603005ACache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executedUNISYS CORP·Filed 1994·Granted Feb 11, 1997·137 cites·60 claims
- 0886US4596977ADual slope analog to digital converter with out-of-range resetHONEYWELL INC·Filed 1984·Granted Jun 24, 1986·34 cites·3 claims
- 0985US7343515B1System and method for performing error recovery in a data processing system having multiple processing partitionsUNISYS CORP·Filed 2004·Granted Mar 11, 2008·53 cites·20 claims
- 1085US6981106B1System and method for accelerating ownership within a directory-based memory systemUNISYS CORP·Filed 2002·Granted Dec 27, 2005·51 cites·45 claims
- 1185US6438659B1Directory based cache coherency system supporting multiple instruction processor and input/output cachesUNISYS CORP·Filed 2000·Granted Aug 20, 2002·38 cites·8 claims
- 1285US5875472AAddress conflict detection system employing address indirection for use in a high-speed multi-processor systemUNISYS CORP·Filed 1997·Granted Feb 23, 1999·127 cites·21 claims
- 1381US7260677B1Programmable system and method for accessing a shared memoryUNISYS CORP·Filed 2003·Granted Aug 21, 2007·31 cites·32 claims
- 1481US6178466B1System for maximizing bandpass on an interface directly coupling two units where the interface has independently operative data and address interconnections, and computer sysem employing same.UNISYS CORP·Filed 1998·Granted Jan 23, 2001·102 cites·30 claims
- 1578US6189078B1System and method for increasing data transfer throughput for cache purge transactions using multiple data response indicators to maintain processor consistencyUNISYS CORP·Filed 1998·Granted Feb 13, 2001·83 cites·19 claims
- 1676US7213109B1System and method for providing speculative ownership of cached data based on history trackingUNISYS CORP·Filed 2002·Granted May 1, 2007·23 cites·28 claims
- 1776US6415364B1High-speed memory storage unit for a multiprocessor system having integrated directory and data storage subsystemsUNISYS CORP·Filed 1997·Granted Jul 2, 2002·80 cites·19 claims
- 1876US5875462AMulti-processor data processing system with multiple second level caches mapable to all of addressable memoryUNISYS CORP·Filed 1995·Granted Feb 23, 1999·91 cites·21 claims
- 1975US6434641B1System for reducing the number of requests presented to a main memory in a memory storage system employing a directory-based caching schemeUNISYS CORP·Filed 1999·Granted Aug 13, 2002·72 cites·19 claims
- 2074US7032079B1System and method for accelerating read requests within a multiprocessor systemUNISYS CORP·Filed 2002·Granted Apr 18, 2006·25 cites·21 claims
- 2174US6052760AComputer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locksUNISYS CORP·Filed 1997·Granted Apr 18, 2000·76 cites·6 claims
- 2274US5960455AScalable cross bar type storage controllerUNISYS CORP·Filed 1996·Granted Sep 28, 1999·72 cites·34 claims
- 2373US6014709AMessage flow protocol for avoiding deadlocksUNISYS CORP·Filed 1997·Granted Jan 11, 2000·71 cites·31 claims
- 2472US6973548B1Data acceleration mechanism for a multiprocessor shared memory systemUNISYS CORP·Filed 2003·Granted Dec 6, 2005·17 cites·40 claims
- 2571US6356991B1Programmable address translation systemUNISYS CORP·Filed 1997·Granted Mar 12, 2002·61 cites·27 claims
- 2671US6167489ASystem and method for bypassing supervisory memory intervention for data transfers between devices having local memoriesUNISYS CORP·Filed 1998·Granted Dec 26, 2000·61 cites·34 claims
- 2771US6122711AMethod of and apparatus for store-in second level cache flushUNISYS CORP·Filed 1997·Granted Sep 19, 2000·53 cites·15 claims
- 2870US6182112B1Method of and apparatus for bandwidth control of transfers via a bi-directional interfaceUNISYS CORP·Filed 1998·Granted Jan 30, 2001·56 cites·46 claims
- 2970US5832304AMemory queue with adjustable priority and conflict detectionUNISYS CORP·Filed 1995·Granted Nov 3, 1998·64 cites·25 claims
- 3069US6336088B1Method and apparatus for synchronizing independently executing test lists for design verificationUNISYS CORP·Filed 1998·Granted Jan 1, 2002·34 cites·20 claims
- 3169US5680571AMulti-processor data processing system with multiple, separate instruction and operand second level cachesUNISYS CORP·Filed 1995·Granted Oct 21, 1997·56 cites·13 claims
- 3268US6728835B1Leaky cache mechanismUNISYS CORP·Filed 2000·Granted Apr 27, 2004·16 cites·17 claims
- 3367US9021454B2Operand and limits optimization for binary translation systemUNISYS CORP·Filed 2012·Granted Apr 28, 2015·4 cites·20 claims
- 3466US6457101B1System and method for providing the speculative return of cached data within a hierarchical memory systemUNISYS CORP·Filed 1999·Granted Sep 24, 2002·52 cites·20 claims
- 3562US6587931B1Directory-based cache coherency system supporting multiple instruction processor and input/output cachesUNISYS CORP·Filed 1997·Granted Jul 1, 2003·35 cites·36 claims
- 3662US6453276B1Method and apparatus for efficiently generating test input for a logic simulatorUNISYS CORP·Filed 1998·Granted Sep 17, 2002·23 cites·20 claims
- 3761US6868482B1Method and apparatus for parallel store-in second level cachingUNISYS CORP·Filed 2000·Granted Mar 15, 2005·7 cites·5 claims
- 3861US6477620B1Cache-level return data by-pass system for a hierarchical memoryUNISYS CORP·Filed 1999·Granted Nov 5, 2002·41 cites·20 claims
- 3961US5875201ASecond level cache having instruction cache parity error controlUNISYS CORP·Filed 1996·Granted Feb 23, 1999·42 cites·20 claims
- 4061US5625892ADynamic power regulator for controlling memory power consumptionFiled 1994·Granted Apr 29, 1997·20 cites·17 claims
- 4160US7167955B1System and method for testing and initializing directory store memoryUNISYS CORP·Filed 2003·Granted Jan 23, 2007·9 cites·55 claims
- 4260US6049845ASystem and method for providing speculative arbitration for transferring dataUNISYS CORP·Filed 1997·Granted Apr 11, 2000·39 cites·9 claims
- 4357US7634709B2Familial correction with non-familial double bit error detectionUNISYS CORP·Filed 2001·Granted Dec 15, 2009·5 cites·15 claims
- 4456US7277825B1Apparatus and method for analyzing performance of a data processing systemUNISYS CORP·Filed 2003·Granted Oct 2, 2007·8 cites·35 claims
- 4555US6226716B1Test driver for use in validating a circuit designUNISYS CORP·Filed 1998·Granted May 1, 2001·35 cites·23 claims
- 4654US5946710ASelectable two-way, four-way double cache interleave schemeUNISYS CORP·Filed 1996·Granted Aug 31, 1999·29 cites·14 claims
- 4754US5915128ASerial speed-matching buffer utilizing plurality of registers where each register selectively receives data from transferring units or sequentially transfers data to another registerUNISYS CORP·Filed 1997·Granted Jun 22, 1999·31 cites·17 claims
- 4851US6199135B1Source synchronous transfer scheme for a high speed memory interfaceUNISYS CORP·Filed 1998·Granted Mar 6, 2001·28 cites·40 claims
- 4948US6279098B1Method of and apparatus for serial dynamic system partitioningUNISYS CORP·Filed 1996·Granted Aug 21, 2001·23 cites·16 claims
- 5045US5875119AComputer performance monitoring using time-division multiplexingUNISYS CORP·Filed 1997·Granted Feb 23, 1999·20 cites·28 claims
Showing the top 50 of 56 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →