Inventor · disambiguated record
Milind B. Girkar
Also filed as: GIRKAR MILIND · GIRKAR MILIND B · GIRKAR MILIND BABURAO
81 granted patents·35 pending applications·561 citations·filing 1998–2024
99Inventor score
Files withINTEL CORP88HUGHES CHRISTOPHER J5OULD-AHMED-VALL ELMOUSTAPHA4SAN ADRIAN JESUS CORBAL2VALENTINE ROBERT2
Top patents by PatentIndex Score
116 records- 0198US11977886B2Systems, methods, and apparatuses for tile storeINTEL CORP·Filed 2022·Granted May 7, 2024·7 cites·20 claims
- 0298US11714642B2Systems, methods, and apparatuses for tile storeINTEL CORP·Filed 2022·Granted Aug 1, 2023·7 cites·19 claims
- 0397US11200055B2Systems, methods, and apparatuses for matrix add, subtract, and multiplyINTEL CORP·Filed 2017·Granted Dec 14, 2021·14 cites·20 claims
- 0497US10146535B2Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2016·Granted Dec 4, 2018·23 cites·22 claims
- 0596US11567765B2Systems, methods, and apparatuses for tile loadINTEL CORP·Filed 2017·Granted Jan 31, 2023·8 cites·20 claims
- 0696US11487541B2Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2020·Granted Nov 1, 2022·4 cites·34 claims
- 0795US11544058B2Systems, apparatuses, and methods for fused multiply addINTEL CORP·Filed 2021·Granted Jan 3, 2023·2 cites·20 claims
- 0895US11526354B2Systems, apparatuses, and methods for fused multiply addINTEL CORP·Filed 2021·Granted Dec 13, 2022·2 cites·20 claims
- 0995US11288069B2Systems, methods, and apparatuses for tile storeINTEL CORP·Filed 2017·Granted Mar 29, 2022·7 cites·17 claims
- 1095US10785028B2Protection of keys and sensitive data from attack within microprocessor architectureINTEL CORP·Filed 2018·Granted Sep 22, 2020·16 cites·20 claims
- 1194US11526353B2Systems, apparatuses, and methods for fused multiply addINTEL CORP·Filed 2021·Granted Dec 13, 2022·2 cites·26 claims
- 1294US11507369B2Systems, apparatuses, and methods for fused multiply addINTEL CORP·Filed 2021·Granted Nov 22, 2022·2 cites·28 claims
- 1394US11169802B2Systems, apparatuses, and methods for fused multiply addINTEL CORP·Filed 2016·Granted Nov 9, 2021·8 cites·10 claims
- 1493US11838418B2Protection of keys and sensitive data from attack within microprocessor architectureINTEL CORP·Filed 2020·Granted Dec 5, 2023·3 cites·17 claims
- 1593US11113053B2Data element comparison processors, methods, systems, and instructionsINTEL CORP·Filed 2019·Granted Sep 7, 2021·8 cites·20 claims
- 1693US8447962B2Gathering and scattering multiple data elementsHUGHES CHRISTOPHER J·Filed 2009·Granted May 21, 2013·36 cites·30 claims
- 1792US12260213B2Systems, methods, and apparatuses for matrix add, subtract, and multiplyINTEL CORP·Filed 2021·Granted Mar 25, 2025·1 cites·18 claims
- 1892US11023231B2Systems and methods for executing a fused multiply-add instruction for complex numbersINTEL CORP·Filed 2016·Granted Jun 1, 2021·8 cites·20 claims
- 1992US9513917B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2014·Granted Dec 6, 2016·10 cites·14 claims
- 2092US2025117221A1Systems, methods, and apparatuses for tile transposeINTEL CORP·Filed 2024·Application pending·0 cites
- 2191US8972698B2Vector conflict instructionsHUGHES CHRISTOPHER J·Filed 2010·Granted Mar 3, 2015·18 cites·23 claims
- 2290US8037465B2Thread-data affinity optimization using compilerINTEL CORP·Filed 2005·Granted Oct 11, 2011·28 cites·19 claims
- 2390US2025004716A1Systems, methods, and apparatuses for tile loadINTEL CORP·Filed 2024·Application pending·0 cites
- 2489US7984431B2Method and apparatus for exploiting thread-level parallelismINTEL CORP·Filed 2007·Granted Jul 19, 2011·20 cites·15 claims
- 2588US2024134644A1Systems, methods, and apparatuses for matrix add, subtract, and multiplyINTEL CORP·Filed 2023·Application pending·0 cites
- 2688US2024427600A1Vector friendly instruction format and execution thereofINTEL CORP·Filed 2024·Application pending·0 cites
- 2787US10853065B2Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2018·Granted Dec 1, 2020·3 cites·22 claims
- 2887US9411592B2Vector address conflict resolution with vector population count functionalityINTEL CORP·Filed 2012·Granted Aug 9, 2016·11 cites·31 claims
- 2987US9244677B2Loop vectorization methods and apparatusINTEL CORP·Filed 2012·Granted Jan 26, 2016·9 cites·15 claims
- 3087US8612949B2Methods and apparatuses for compiler-creating helper threads for multi-threadingLIAO SHIH-WEI·Filed 2009·Granted Dec 17, 2013·18 cites·12 claims
- 3187US7571301B2Fast lock-free post-wait synchronization for exploiting parallelism on multi-core processorsINTEL CORP·Filed 2006·Granted Aug 4, 2009·23 cites·27 claims
- 3285US12182571B2Systems, methods, and apparatuses for tile load, multiplication and accumulationINTEL CORP·Filed 2023·Granted Dec 31, 2024·0 cites·20 claims
- 3384US12086594B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2023·Granted Sep 10, 2024·0 cites·23 claims
- 3483US9411584B2Methods, apparatus, instructions, and logic to provide vector address conflict detection functionalityINTEL CORP·Filed 2012·Granted Aug 9, 2016·7 cites·37 claims
- 3583US7020873B2Apparatus and method for vectorization of detected saturation and clipping operations in serial code loops of a source programINTEL CORP·Filed 2002·Granted Mar 28, 2006·33 cites·30 claims
- 3683US2025060963A1Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2024·Application pending·0 cites
- 3782US12124846B2Systems, apparatuses, and methods for addition of partial productsINTEL CORP·Filed 2023·Granted Oct 22, 2024·0 cites·7 claims
- 3882US9898266B2Loop vectorization methods and apparatusINTEL CORP·Filed 2016·Granted Feb 20, 2018·3 cites·20 claims
- 3980US8719839B2Two way communication support for heterogenous processors of a computer platformYAN SHOUMENG·Filed 2009·Granted May 6, 2014·13 cites·40 claims
- 4080US7398521B2Methods and apparatuses for thread management of multi-threadingINTEL CORP·Filed 2004·Granted Jul 8, 2008·26 cites·14 claims
- 4179US11782709B2Systems, apparatuses, and methods for addition of partial productsINTEL CORP·Filed 2022·Granted Oct 10, 2023·0 cites·20 claims
- 4279US11036499B2Systems, apparatuses, and methods for controllable sine and/or cosine operationsINTEL CORP·Filed 2017·Granted Jun 15, 2021·2 cites·20 claims
- 4379US7487502B2Programmable event driven yield mechanism which may activate other threadsINTEL CORP·Filed 2003·Granted Feb 3, 2009·19 cites·37 claims
- 4478US7657880B2Safe store for speculative helper threadsINTEL CORP·Filed 2003·Granted Feb 2, 2010·26 cites·30 claims
- 4577US12073214B2Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2022·Granted Aug 27, 2024·0 cites·23 claims
- 4676US11740904B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2021·Granted Aug 29, 2023·0 cites·20 claims
- 4776US10459858B2Programmable event driven yield mechanism which may activate other threadsINTEL CORP·Filed 2017·Granted Oct 29, 2019·1 cites·14 claims
- 4876US2024126546A1Systems and methods for executing a fused multiply-add instruction for complex numbersINTEL CORP·Filed 2023·Application pending·0 cites
- 4975US10877910B2Programmable event driven yield mechanism which may activate other threadsINTEL CORP·Filed 2017·Granted Dec 29, 2020·1 cites·10 claims
- 5073US11210096B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2020·Granted Dec 28, 2021·0 cites·28 claims
Showing the top 50 of 116 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →