Inventor · disambiguated record
Michael S. Gray
Also filed as: GRAY MICHAEL · GRAY MICHAEL S · GRAY MICHAEL STEWART · GRAY MICHAEL W
25 granted patents·5 pending applications·594 citations·filing 1997–2022
96Inventor score
Top patents by PatentIndex Score
30 records- 0198US7484197B2Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designsIBM·Filed 2006·Granted Jan 27, 2009·297 cites·20 claims
- 0297US7503020B2IC layout optimization to improve yieldIBM·Filed 2006·Granted Mar 10, 2009·110 cites·15 claims
- 0395US9158885B1Reducing color conflicts in triple patterning lithographyIBM·Filed 2014·Granted Oct 13, 2015·52 cites·20 claims
- 0491US6013225ASurface densification of machine components made by powder metallurgyZENITH SINTERED PRODUCTS INC·Filed 1997·Granted Jan 11, 2000·42 cites·14 claims
- 0590US11308257B1Stacked via rivets in chip hotspotsIBM·Filed 2020·Granted Apr 19, 2022·2 cites·17 claims
- 0685US10885260B1Fin-based fill cell optimizationIBM·Filed 2019·Granted Jan 5, 2021·4 cites·20 claims
- 0779US9971861B2Selective boundary overlay insertion for hierarchical circuit designIBM·Filed 2016·Granted May 15, 2018·3 cites·14 claims
- 0879US7761818B2Obtaining a feasible integer solution in a hierarchical circuit layout optimizationIBM·Filed 2007·Granted Jul 20, 2010·10 cites·15 claims
- 0978US8302062B2Methods to obtain a feasible integer solution in a hierarchical circuit layout optimizationGRAY MICHAEL S·Filed 2010·Granted Oct 30, 2012·6 cites·15 claims
- 1076US12138634B2Mill liner, coupling tool and method of removal of a mill linerBRADKEN RESOURCES PTY LTD·Filed 2019·Granted Nov 12, 2024·1 cites·22 claims
- 1174US8296706B2Handling two-dimensional constraints in integrated circuit layoutGRAY MICHAEL S·Filed 2010·Granted Oct 23, 2012·4 cites·20 claims
- 1271US7062729B2Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimizationIBM·Filed 2004·Granted Jun 13, 2006·16 cites·17 claims
- 1370US7895562B2Adaptive weighting method for layout optimization with multiple prioritiesIBM·Filed 2007·Granted Feb 22, 2011·5 cites·6 claims
- 1470US7260790B2Integrated circuit yield enhancement using Voronoi diagramsIBM·Filed 2004·Granted Aug 21, 2007·15 cites·33 claims
- 1569US7735042B2Context aware sub-circuit layout modificationIBM·Filed 2007·Granted Jun 8, 2010·4 cites·20 claims
- 1666US8555229B2Parallel solving of layout optimizationTANG XIAOPING·Filed 2011·Granted Oct 8, 2013·2 cites·20 claims
- 1765US7865848B2Layout optimization using parameterized cellsIBM·Filed 2007·Granted Jan 4, 2011·3 cites·2 claims
- 1864US7818694B2IC layout optimization to improve yieldIBM·Filed 2008·Granted Oct 19, 2010·2 cites·20 claims
- 1964US7490308B2Method for implementing overlay-based modification of VLSI design layoutIBM·Filed 2006·Granted Feb 10, 2009·4 cites·6 claims
- 2061US11055465B2Fill techniques for avoiding Boolean DRC failures during cell placementIBM·Filed 2019·Granted Jul 6, 2021·0 cites·20 claims
- 2161US7117456B2Circuit area minimization using scalingIBM·Filed 2003·Granted Oct 3, 2006·7 cites·20 claims
- 2257US11822867B2Hierarchical color decomposition of process layers with shape and orientation requirementsIBM·Filed 2021·Granted Nov 21, 2023·0 cites·20 claims
- 2357US7120887B2Cloned and original circuit shape mergingIBM·Filed 2004·Granted Oct 10, 2006·5 cites·20 claims
- 2456US12112114B2Hierarchical color decomposition of library cells with boundary-aware color selectionIBM·Filed 2021·Granted Oct 8, 2024·0 cites·20 claims
- 2544US2024246087A1Coupling for a grinding mill linerBRADKEN RESOURCES PTY LTD·Filed 2022·Application pending·0 cites
- 2644US2009037850A1Polygonal area design rule correction method for vlsi layoutsGRAY MICHAEL S·Filed 2007·Application pending·0 cites
- 2744US2008172638A1Method of optimizing hierarchical very large scale integration (vlsi) design by use of cluster-based logic cell cloningGRAY MICHAEL S·Filed 2007·Application pending·0 cites
- 2839US2006294511A1Method, system, and computer program product for deploying different versions of software in a single packageIBM·Filed 2005·Application pending·0 cites
- 2939US2012233576A1Schematic-based layout migrationBARROWS GEOFFREY R·Filed 2011·Application pending·0 cites
- 3033US8448124B2Post timing layout modification for performanceFASSNACHT UWE·Filed 2011·Granted May 21, 2013·0 cites·20 claims
Join the waitlist — get patent alerts
Get an alert when Michael S. Gray files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →