Inventor · disambiguated record
Mihalis Michael
Also filed as: MICHAEL MIHALIS · MICHAEL MIHALIS KOLIOS
11 granted patents·8 pending applications·348 citations·filing 1999–2024
90Inventor score
Files withVOLTERRA SEMICONDUCTOR CORP4INFINEON TECH CANADA INC2KAMATH ARVIND2TRAN KHANH2MAXIM INTEGRATED PRODUCTS1
Top patents by PatentIndex Score
19 records- 0194US6778390B2High-performance heat sink for printed circuit boardsNVIDIA CORP·Filed 2001·Granted Aug 17, 2004·124 cites·23 claims
- 0292US9099340B2Power management applications of interconnect substratesVOLTERRA SEMICONDUCTOR CORP·Filed 2012·Granted Aug 4, 2015·12 cites·37 claims
- 0388US9520342B2Power management applications of interconnect substratesVOLTERRA SEMICONDUCTOR CORP·Filed 2015·Granted Dec 13, 2016·5 cites·19 claims
- 0488US6214640B1Method of manufacturing a plurality of semiconductor packagesTESSERA INC·Filed 1999·Granted Apr 10, 2001·119 cites·26 claims
- 0587US6555759B2Interconnect structureFiled 2001·Granted Apr 29, 2003·34 cites·16 claims
- 0685US6230400B1Method for forming interconnectsFiled 1999·Granted May 15, 2001·51 cites·41 claims
- 0774US2025140896A1Printed adhesive for high volumetric energy density in solid state batteries, and methods of making and using the sameKAMATH ARVIND·Filed 2024·Application pending·0 cites
- 0874US2025140916A1Printed layers for encapsulation and redistribution in solid state batteries, and methods of making and using the sameKAMATH ARVIND·Filed 2024·Application pending·0 cites
- 0970US10332827B2Power management application of interconnect substratesVOLTERRA SEMICONDUCTOR CORP·Filed 2016·Granted Jun 25, 2019·1 cites·25 claims
- 1066US2023420731A1High energy-density solid-state battery, and method(s) of making the sameTRAN KHANH·Filed 2023·Application pending·0 cites
- 1166US2023378606A1Passivation/encapsulation layer, via and distribution layer, solid-state battery including the same, and method(s) of making the sameTRAN KHANH·Filed 2023·Application pending·0 cites
- 1265US2024113341A1Cylindrical solid-state battery, and methods of making and using the sameVAN DER LINDE RICHARD·Filed 2023·Application pending·0 cites
- 1362US10748845B2Power management application of interconnect substratesVOLTERRA SEMICONDUCTOR CORP·Filed 2019·Granted Aug 18, 2020·0 cites·20 claims
- 1462US9070662B2Chip-scale packaging with protective heat spreaderMICHAEL MIHALIS·Filed 2010·Granted Jun 30, 2015·2 cites·64 claims
- 1558US2025140665A1Leaded package using routing layer for integrated circuit dieINFINEON TECH CANADA INC·Filed 2023·Application pending·0 cites
- 1654US11296019B1Vertically structured pad systemMAXIM INTEGRATED PRODUCTS·Filed 2020·Granted Apr 5, 2022·0 cites·20 claims
- 1754US2025140674A1Multi-die packageINFINEON TECH CANADA INC·Filed 2023·Application pending·0 cites
- 1848US9806001B2Chip-scale packaging with protective heat spreaderVolterra Semiconductor LLC·Filed 2015·Granted Oct 31, 2017·0 cites·7 claims
- 1933US2001018800A1Method for forming interconnectsFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →