Inventor · disambiguated record
Michael Thaithanh Phan
Also filed as: PHAN MICHAEL · PHAN MICHAEL THAITHANH
17 granted patents·1 pending application·179 citations·filing 2001–2020
93Inventor score
Top patents by PatentIndex Score
18 records- 0191US8724373B2Apparatus for selective word-line boost on a memory cellGARG MANISH·Filed 2012·Granted May 13, 2014·16 cites·40 claims
- 0291US6385071B1Redundant scheme for CAMRAM memory arrayIBM·Filed 2001·Granted May 7, 2002·65 cites·18 claims
- 0389US8730713B2SRAM cell writabilityGARG MANISH·Filed 2012·Granted May 20, 2014·14 cites·22 claims
- 0481US8659972B2Adaptive read wordline voltage boosting apparatus and method for multi-port SRAMPHAN MICHAEL THAITHANH·Filed 2012·Granted Feb 25, 2014·9 cites·28 claims
- 0580US6452822B1Segmented match line arrangement for content addressable memoryIBM·Filed 2001·Granted Sep 17, 2002·29 cites·30 claims
- 0673US8824230B2Method and apparatus of reducing leakage power in multiple port SRAM memory cellPHAN MICHAEL THAITHANH·Filed 2011·Granted Sep 2, 2014·5 cites·58 claims
- 0768US7961499B2Low leakage high performance static random access memory cell using dual-technology transistorsQUALCOMM INC·Filed 2009·Granted Jun 14, 2011·5 cites·19 claims
- 0868US7952901B2Content addressable memoryQUALCOMM INC·Filed 2007·Granted May 31, 2011·4 cites·34 claims
- 0967US7616468B2Method and apparatus for reducing power consumption in a content addressable memoryQUALCOMM INC·Filed 2006·Granted Nov 10, 2009·5 cites·20 claims
- 1066US7242600B2Circuit and method for subdividing a CAMRAM bank by controlling a virtual groundQUALCOMM INC·Filed 2005·Granted Jul 10, 2007·6 cites·21 claims
- 1165US7586772B2Method and apparatus for aborting content addressable memory search operationsQUALCOMM INC·Filed 2006·Granted Sep 8, 2009·5 cites·6 claims
- 1264US7761774B2High speed CAM lookup using stored encoded keyQUALCOMM INC·Filed 2005·Granted Jul 20, 2010·5 cites·27 claims
- 1361US6816396B2Apparatus for detecting multiple hits in a CAMRAM memory arrayIBM·Filed 2003·Granted Nov 9, 2004·11 cites·14 claims
- 1456US11367480B2Memory device implementing multiple port readMARVELL ASIA PTE LTD·Filed 2020·Granted Jun 21, 2022·0 cites·20 claims
- 1541US8576612B2Low leakage high performance static random access memory cell using dual-technology transistorsGARG MANISH·Filed 2011·Granted Nov 5, 2013·0 cites·21 claims
- 1638US10559352B2Bitline-driven sense amplifier clocking schemeQUALCOMM INC·Filed 2018·Granted Feb 11, 2020·0 cites·28 claims
- 1733US2011227639A1Method and Apparatus for Suppressing Bitline Coupling Through Miller Capacitance to a Sense Amplifier Interstitial NodeQUALCOMM INC·Filed 2010·Application pending·0 cites
- 1831US10541044B2Providing efficient handling of memory array failures in processor-based systemsQUALCOMM INC·Filed 2017·Granted Jan 21, 2020·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →