Inventor · disambiguated record
Ming Y. Siu
Also filed as: SIU MING Y · SIU MING Y (MICHAEL) · SIU MING YIU · SIU MING YIU ANDY
58 granted patents·7 pending applications·826 citations·filing 2004–2025
98Inventor score
Top patents by PatentIndex Score
65 records- 0198US10338919B2Generalized acceleration of matrix multiply accumulate operationsNVIDIA CORP·Filed 2017·Granted Jul 2, 2019·24 cites·20 claims
- 0297US7680988B1Single interconnect providing read and write access to a memory shared by concurrent threadsNVIDIA CORP·Filed 2006·Granted Mar 16, 2010·101 cites·21 claims
- 0396US8108625B1Shared memory with parallel access and access conflict resolution mechanismCOON BRETT W·Filed 2006·Granted Jan 31, 2012·73 cites·19 claims
- 0496US7434032B1Tracking register usage during multithreaded processing using a scoreboard having separate memory regions and storing sequential register size indicatorsNVIDIA CORP·Filed 2005·Granted Oct 7, 2008·52 cites·13 claims
- 0595US11816482B2Generalized acceleration of matrix multiply accumulate operationsNVIDIA CORP·Filed 2022·Granted Nov 14, 2023·2 cites·20 claims
- 0695US7634621B1Register file allocationNVIDIA CORP·Filed 2006·Granted Dec 15, 2009·45 cites·24 claims
- 0794US11392829B1Managing data sparsity for neural networksNVIDIA CORP·Filed 2019·Granted Jul 19, 2022·35 cites·20 claims
- 0894US8266383B1Cache miss processing using a defer/replay mechanismMINKIN ALEXANDER L·Filed 2009·Granted Sep 11, 2012·51 cites·20 claims
- 0994US8037119B1Multipurpose functional unit with single-precision and double-precision operationsNVIDIA CORP·Filed 2006·Granted Oct 11, 2011·44 cites·17 claims
- 1092US10884734B2Generalized acceleration of matrix multiply accumulate operationsNVIDIA CORP·Filed 2019·Granted Jan 5, 2021·5 cites·20 claims
- 1192US8176265B2Shared single-access memory with management of multiple parallel requestsCOON BRETT W·Filed 2011·Granted May 8, 2012·16 cites·8 claims
- 1291US8051123B1Multipurpose functional unit with double-precision and filtering operationsNVIDIA CORP·Filed 2006·Granted Nov 1, 2011·26 cites·18 claims
- 1391US7428566B2Multipurpose functional unit with multiply-add and format conversion pipelineNVIDIA CORP·Filed 2004·Granted Sep 23, 2008·68 cites·21 claims
- 1490US7834881B2Operand collector architectureNVIDIA CORP·Filed 2006·Granted Nov 16, 2010·22 cites·20 claims
- 1589US8174531B1Programmable graphics processor for multithreaded execution of programsLINDHOLM JOHN ERIK·Filed 2009·Granted May 8, 2012·16 cites·10 claims
- 1689US7484076B1Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q<P)NVIDIA CORP·Filed 2006·Granted Jan 27, 2009·22 cites·19 claims
- 1788US8106914B2Fused multiply-add functional unitOBERMAN STUART·Filed 2007·Granted Jan 31, 2012·28 cites·17 claims
- 1886US7225323B2Multi-purpose floating point and integer multiply-add functional unit with multiplication-comparison test addition and exponent pipelinesNVIDIA CORP·Filed 2004·Granted May 29, 2007·43 cites·23 claims
- 1985US8405665B2Programmable graphics processor for multithreaded execution of programsLINDHOLM JOHN ERIK·Filed 2012·Granted Mar 26, 2013·7 cites·15 claims
- 2085US2025362910A1Generalized acceleration of matrix multiply accumulate operationsNVIDIA CORP·Filed 2025·Application pending·0 cites
- 2183US12399716B2Inline data inspection for workload simplificationNVIDIA CORP·Filed 2024·Granted Aug 26, 2025·0 cites·20 claims
- 2283US7640285B1Multipurpose arithmetic functional unitNVIDIA CORP·Filed 2004·Granted Dec 29, 2009·35 cites·19 claims
- 2381US12321743B2Generalized acceleration of matrix multiply accumulate operationsNVIDIA CORP·Filed 2023·Granted Jun 3, 2025·0 cites·20 claims
- 2481US9830197B2Cooperative thread array reduction and scan operationsNVIDIA CORP·Filed 2016·Granted Nov 28, 2017·2 cites·20 claims
- 2581US9659339B2Programmable graphics processor for multithreaded execution of programsNVIDIA CORP·Filed 2013·Granted May 23, 2017·5 cites·23 claims
- 2679US11977888B2Inline data inspection for workload simplificationNVIDIA CORP·Filed 2023·Granted May 7, 2024·0 cites·20 claims
- 2779US8522000B2Trap handler architecture for a parallel processing unitSHEBANOW MICHAEL C·Filed 2009·Granted Aug 27, 2013·11 cites·20 claims
- 2878US10217184B2Programmable graphics processor for multithreaded execution of programsNVIDIA CORP·Filed 2017·Granted Feb 26, 2019·2 cites·20 claims
- 2978US8225076B1Scoreboard having size indicators for tracking sequential destination register usage in a multi-threaded processorCOON BRETT W·Filed 2008·Granted Jul 17, 2012·7 cites·18 claims
- 3077US9477482B2System, method, and computer program product for implementing multi-cycle register file bypassNVIDIA CORP·Filed 2013·Granted Oct 25, 2016·4 cites·20 claims
- 3176US11816481B2Generalized acceleration of matrix multiply accumulate operationsNVIDIA CORP·Filed 2022·Granted Nov 14, 2023·0 cites·20 claims
- 3275US8533435B2Reordering operands assigned to each one of read request ports concurrently accessing multibank register file to avoid bank conflictQIU XIAOGANG·Filed 2010·Granted Sep 10, 2013·4 cites·19 claims
- 3373US11797302B2Generalized acceleration of matrix multiply accumulate operationsNVIDIA CORP·Filed 2021·Granted Oct 24, 2023·0 cites·23 claims
- 3473US11797303B2Generalized acceleration of matrix multiply accumulate operationsNVIDIA CORP·Filed 2021·Granted Oct 24, 2023·0 cites·23 claims
- 3573US11233738B1Dynamic performance configuration for data traffic workflowsAMAZON TECH INC·Filed 2020·Granted Jan 25, 2022·1 cites·20 claims
- 3673US7339592B2Simulating multiported memories using lower port count memoriesNVIDIA CORP·Filed 2004·Granted Mar 4, 2008·17 cites·21 claims
- 3772US11797301B2Generalized acceleration of matrix multiply accumulate operationsNVIDIA CORP·Filed 2021·Granted Oct 24, 2023·0 cites·20 claims
- 3871US8190669B1Multipurpose arithmetic functional unitOBERMAN STUART F·Filed 2004·Granted May 29, 2012·21 cites·18 claims
- 3970US8539204B2Cooperative thread array reduction and scan operationsFAHS BRIAN·Filed 2010·Granted Sep 17, 2013·2 cites·15 claims
- 4070US7366745B1High-speed function approximationNVIDIA CORP·Filed 2004·Granted Apr 29, 2008·14 cites·22 claims
- 4169US11489541B2Compression techniques for data structures suitable for artificial neural networksNVIDIA CORP·Filed 2019·Granted Nov 1, 2022·2 cites·28 claims
- 4268US11609761B2Inline data inspection for workload simplificationNVIDIA CORP·Filed 2019·Granted Mar 21, 2023·0 cites·30 claims
- 4367US11379708B2Techniques for efficiently operating a processing system based on energy characteristics of instructions and machine learningNVIDIA CORP·Filed 2019·Granted Jul 5, 2022·1 cites·25 claims
- 4467US9417875B2Cooperative thread array reduction and scan operationsNVIDIA CORP·Filed 2013·Granted Aug 16, 2016·1 cites·10 claims
- 4566US9829956B2Approach to power reduction in floating-point operationsNVIDIA CORP·Filed 2012·Granted Nov 28, 2017·2 cites·20 claims
- 4666US8850436B2Opcode-specified predicatable warp post-synchronizationFAHS BRIAN·Filed 2010·Granted Sep 30, 2014·2 cites·22 claims
- 4764US11379420B2Decompression techniques for processing compressed data suitable for artificial neural networksNVIDIA CORP·Filed 2019·Granted Jul 5, 2022·1 cites·22 claims
- 4861US10503507B2Inline data inspection for workload simplificationNVIDIA CORP·Filed 2017·Granted Dec 10, 2019·0 cites·14 claims
- 4961US10255228B2System and method for performing shaped memory access operationsQIU XIAOGANG·Filed 2011·Granted Apr 9, 2019·1 cites·7 claims
- 5061US7240184B2Multipurpose functional unit with multiplication pipeline, addition pipeline, addition pipeline and logical test pipeline capable of performing integer multiply-add operationsNVIDIA CORP·Filed 2004·Granted Jul 3, 2007·7 cites·21 claims
Showing the top 50 of 65 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →