Inventor · disambiguated record
Milind Sonawane
Also filed as: SONAWANE MILIND · SONAWANE MILIND BHAIYYASAHEB
17 granted patents·2 pending applications·36 citations·filing 2004–2025
91Inventor score
Top patents by PatentIndex Score
19 records- 0189US10281524B2Test partition external input/output interface control for test partitions in a semiconductorNVIDIA CORP·Filed 2016·Granted May 7, 2019·6 cites·12 claims
- 0287US10317463B2Scan system interface (SSI) moduleNVIDIA CORP·Filed 2016·Granted Jun 11, 2019·6 cites·18 claims
- 0381US9222981B2Global low power capture scheme for coresNVIDIA CORP·Filed 2012·Granted Dec 29, 2015·5 cites·20 claims
- 0480US9377510B2System for reducing peak power during scan shift at the global level for scan based testsNVIDIA CORP·Filed 2012·Granted Jun 28, 2016·5 cites·16 claims
- 0578US10444280B2Independent test partition clock coordination across multiple test partitionsNVIDIA CORP·Filed 2016·Granted Oct 15, 2019·2 cites·20 claims
- 0678US9395414B2System for reducing peak power during scan shift at the local level for scan based testsNVIDIA CORP·Filed 2012·Granted Jul 19, 2016·4 cites·22 claims
- 0773US2025222941A1Localized in-system testing for autonomous and semi-autonomous systems and applicationsNVIDIA CORP·Filed 2025·Application pending·0 cites
- 0872US12291219B2Asynchronous in-system testing for autonomous systems and applicationsNVIDIA CORP·Filed 2022·Granted May 6, 2025·0 cites·19 claims
- 0971US10746798B1Field adaptable in-system test mechanismsNVIDIA CORP·Filed 2019·Granted Aug 18, 2020·1 cites·18 claims
- 1065US10890620B2On-chip execution of in-system test utilizing a generalized test imageNVIDIA CORP·Filed 2019·Granted Jan 12, 2021·1 cites·18 claims
- 1158US10545189B2Granular dynamic test systems and methodsNVIDIA CORP·Filed 2016·Granted Jan 28, 2020·0 cites·25 claims
- 1255US10473720B2Dynamic independent test partition clockNVIDIA CORP·Filed 2016·Granted Nov 12, 2019·0 cites·12 claims
- 1355US10451676B2Method and system for dynamic standard test access (DSTA) for a logic block reuseNVIDIA CORP·Filed 2016·Granted Oct 22, 2019·0 cites·20 claims
- 1450US9829536B2Performing on-chip partial good die identificationNVIDIA CORP·Filed 2016·Granted Nov 28, 2017·0 cites·19 claims
- 1549US11668750B2Performing testing utilizing staggered clocksNVIDIA CORP·Filed 2021·Granted Jun 6, 2023·0 cites·18 claims
- 1649US10481203B2Granular dynamic test systems and methodsNVIDIA CORP·Filed 2017·Granted Nov 19, 2019·0 cites·20 claims
- 1746US7334172B2Transition fault detection register with extended shift modeLSI LOGIC CORP·Filed 2004·Granted Feb 19, 2008·6 cites·14 claims
- 1844US9885753B2Scan systems and methodsNVIDIA CORP·Filed 2013·Granted Feb 6, 2018·0 cites·18 claims
- 1939US2022365857A1Runtime in-system testingNVIDIA CORP·Filed 2021·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →