Inventor · disambiguated record
Mohammad Abdallah
Also filed as: ABDALLAH MOHAMMAD · ABDALLAH MOHAMMAD A · ABDALLAH MOHAMMAD A F F · ABDALLAH MOHAMMAD ABDEL-FATTAH
62 granted patents·26 pending applications·401 citations·filing 1993–2021
98Inventor score
Files withINTEL CORP39SOFT MACHINES INC21ABDALLAH MOHAMMAD10AVUDAIYAPPAN KARTHIKEYAN5ABDALLAH MOHAMMAD A3
Top patents by PatentIndex Score
88 records- 0197US9053292B2Processor executing super instruction matrix with register file configurable for single or multiple threads operationsSOFT MACHINES INC·Filed 2012·Granted Jun 9, 2015·36 cites·17 claims
- 0297US8930674B2Systems and methods for accessing a unified translation lookaside bufferAVUDAIYAPPAN KARTHIKEYAN·Filed 2012·Granted Jan 6, 2015·62 cites·20 claims
- 0395US9811377B2Method for executing multithreaded instructions grouped into blocksINTEL CORP·Filed 2014·Granted Nov 7, 2017·23 cites·14 claims
- 0495US8677105B2Parallel processing of a sequential program using hardware generated threads and their instruction groups executing on plural execution units and accessing register file segments using dependency inheritance vectors across multiple enginesABDALLAH MOHAMMAD A·Filed 2007·Granted Mar 18, 2014·45 cites·11 claims
- 0595US8327115B2Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate modeABDALLAH MOHAMMAD A·Filed 2007·Granted Dec 4, 2012·41 cites·16 claims
- 0694US9823930B2Method for emulating a guest centralized flag architecture by using a native distributed flag architectureINTEL CORP·Filed 2014·Granted Nov 21, 2017·17 cites·15 claims
- 0793US10289605B2Apparatus and method for processing an instruction matrix specifying parallel and dependent operationsINTEL CORP·Filed 2017·Granted May 14, 2019·6 cites·20 claims
- 0893US9207960B2Multilevel conversion table cache for translating guest instructions to native instructionsABDALLAH MOHAMMAD·Filed 2012·Granted Dec 8, 2015·18 cites·21 claims
- 0990US9733942B2Mapping of guest instruction block assembled according to branch prediction to translated native conversion blockABDALLAH MOHAMMAD·Filed 2012·Granted Aug 15, 2017·10 cites·22 claims
- 1089US9542187B2Guest instruction block with near branching and far branching sequence construction to native instruction blockABDALLAH MOHAMMAD·Filed 2012·Granted Jan 10, 2017·10 cites·21 claims
- 1188US9858080B2Method for implementing a reduced size register view data structure in a microprocessorINTEL CORP·Filed 2014·Granted Jan 2, 2018·9 cites·18 claims
- 1288US9575762B2Method for populating register view data structure by using register template snapshotsSOFT MACHINES INC·Filed 2014·Granted Feb 21, 2017·9 cites·18 claims
- 1385US9921845B2Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable enginesINTEL CORP·Filed 2016·Granted Mar 20, 2018·3 cites·20 claims
- 1484US9733909B2System converter that implements a reordering process through JIT (just in time) optimization that ensures loads do not dispatch ahead of other loads that are to the same addressINTEL CORP·Filed 2015·Granted Aug 15, 2017·4 cites·17 claims
- 1583US9990200B2Executing instruction sequence code blocks by using virtual cores instantiated by partitionable enginesINTEL CORP·Filed 2016·Granted Jun 5, 2018·3 cites·19 claims
- 1680US10255076B2Method for performing dual dispatch of blocks and half blocksINTEL CORP·Filed 2017·Granted Apr 9, 2019·2 cites·18 claims
- 1779US10521239B2Microprocessor accelerated code optimizerINTEL CORP·Filed 2016·Granted Dec 31, 2019·2 cites·20 claims
- 1878US9710387B2Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processorABDALLAH MOHAMMAD·Filed 2012·Granted Jul 18, 2017·4 cites·20 claims
- 1978US9274793B2Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable enginesABDALLAH MOHAMMAD·Filed 2012·Granted Mar 1, 2016·3 cites·24 claims
- 2077US10310987B2Systems and methods for accessing a unified translation lookaside bufferINTEL CORP·Filed 2017·Granted Jun 4, 2019·1 cites·20 claims
- 2177US9424046B2Systems and methods for load canceling in a processor that is connected to an external interconnect fabricAVUDAIYAPPAN KARTHIKEYAN·Filed 2012·Granted Aug 23, 2016·3 cites·21 claims
- 2276US9229873B2Systems and methods for supporting a plurality of load and store accesses of a cacheAVUDAIYAPPAN KARTHIKEYAN·Filed 2012·Granted Jan 5, 2016·3 cites·20 claims
- 2374US11281481B2Using a plurality of conversion tables to implement an instruction set agnostic runtime architectureINTEL CORP·Filed 2015·Granted Mar 22, 2022·2 cites·20 claims
- 2474US9639364B2Guest to native block address mappings and management of native code storageABDALLAH MOHAMMAD·Filed 2012·Granted May 2, 2017·3 cites·27 claims
- 2574US9501280B2Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to referSOFT MACHINES INC·Filed 2014·Granted Nov 22, 2016·2 cites·17 claims
- 2673US10191746B2Accelerated code optimizer for a multiengine microprocessorABDALLAH MOHAMMAD·Filed 2011·Granted Jan 29, 2019·3 cites·14 claims
- 2772US10042643B2Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processorINTEL CORP·Filed 2016·Granted Aug 7, 2018·1 cites·20 claims
- 2869US9720839B2Systems and methods for supporting a plurality of load and store accesses of a cacheINTEL CORP·Filed 2015·Granted Aug 1, 2017·1 cites·18 claims
- 2968US10228949B2Single cycle multi-branch prediction including shadow cache for early far branch predictionABDALLAH MOHAMMAD·Filed 2011·Granted Mar 12, 2019·2 cites·24 claims
- 3067US8342076B2Brake actuator and method of forming the sameINDIAN HEAD INC·Filed 2008·Granted Jan 1, 2013·4 cites·27 claims
- 3166US9891915B2Method and apparatus to increase the speed of the load access and data return speed path using early lower address bitsINTEL CORP·Filed 2014·Granted Feb 13, 2018·1 cites·18 claims
- 3263US10713047B2Fast unaligned memory accessINTEL CORP·Filed 2019·Granted Jul 14, 2020·0 cites·20 claims
- 3363US10564975B2Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable enginesINTEL CORP·Filed 2018·Granted Feb 18, 2020·0 cites·14 claims
- 3463US9934042B2Method for dependency broadcasting through a block organized source view data structureINTEL CORP·Filed 2014·Granted Apr 3, 2018·1 cites·20 claims
- 3562US10884739B2Systems and methods for load canceling in a processor that is connected to an external interconnect fabricINTEL CORP·Filed 2018·Granted Jan 5, 2021·0 cites·7 claims
- 3662US5469376ADigital circuit for the evaluation of mathematical expressionsFiled 1993·Granted Nov 21, 1995·39 cites·8 claims
- 3760US9965281B2Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to referINTEL CORP·Filed 2016·Granted May 8, 2018·0 cites·12 claims
- 3860USD435050SReciprocating compressorINGERSOLL RAND CO·Filed 1999·Granted Dec 12, 2000·11 cites·1 claims
- 3960US2022068500A1Systems and methods for privately and securely tracking location data and biometric sampling for tracing disease propagationABDALLAH MOHAMMAD ABDEL FATTAH·Filed 2021·Application pending·0 cites
- 4059US10810014B2Method and apparatus for guest return address stack emulation supporting speculationINTEL CORP·Filed 2019·Granted Oct 20, 2020·0 cites·21 claims
- 4159US9767038B2Systems and methods for accessing a unified translation lookaside bufferINTEL CORP·Filed 2016·Granted Sep 19, 2017·0 cites·20 claims
- 4259US2017364476A1Instruction and logic for performing a dot-product operationINTEL CORP·Filed 2017·Application pending·0 cites
- 4358US10503514B2Method for implementing a reduced size register view data structure in a microprocessorINTEL CORP·Filed 2017·Granted Dec 10, 2019·0 cites·20 claims
- 4458US10303484B2Method for implementing a line speed interconnect structureINTEL CORP·Filed 2017·Granted May 28, 2019·0 cites·20 claims
- 4558US10282170B2Method for a stage optimized high speed adderINTEL CORP·Filed 2017·Granted May 7, 2019·0 cites·20 claims
- 4658US10013254B2Systems and methods for load cancelling in a processor that is connected to an external interconnect fabricINTEL CORP·Filed 2016·Granted Jul 3, 2018·0 cites·18 claims
- 4758US9921850B2Instruction sequence buffer to enhance branch prediction efficiencyINTEL CORP·Filed 2016·Granted Mar 20, 2018·0 cites·20 claims
- 4857US10146576B2Method for executing multithreaded instructions grouped into blocksINTEL CORP·Filed 2017·Granted Dec 4, 2018·0 cites·20 claims
- 4957US9886416B2Apparatus and method for processing an instruction matrix specifying parallel and dependent operationsINTEL CORP·Filed 2015·Granted Feb 6, 2018·0 cites·14 claims
- 5057US9740499B2Method for implementing a line speed interconnect structureINTEL CORP·Filed 2014·Granted Aug 22, 2017·0 cites·21 claims
Showing the top 50 of 88 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →