Inventor · disambiguated record
Mohit Kapur
Also filed as: KAPUR MOHIT
25 granted patents·3 pending applications·97 citations·filing 2003–2023
95Inventor score
Top patents by PatentIndex Score
28 records- 0193US10298545B2Secure processing environment for protecting sensitive informationIBM·Filed 2013·Granted May 21, 2019·15 cites·13 claims
- 0292US10705556B2Phase continuous signal generation using direct digital synthesisIBM·Filed 2017·Granted Jul 7, 2020·12 cites·25 claims
- 0383US9230046B2Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware acceleratorASAAD SAMETH W·Filed 2012·Granted Jan 5, 2016·15 cites·25 claims
- 0483US7509568B2Error type identification circuit for identifying different types of errors in communications devicesIBM·Filed 2005·Granted Mar 24, 2009·14 cites·14 claims
- 0582US11093674B2Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware acceleratorIBM·Filed 2018·Granted Aug 17, 2021·2 cites·20 claims
- 0682US10547596B2Secure processing environment for protecting sensitive informationIBM·Filed 2019·Granted Jan 28, 2020·2 cites·20 claims
- 0781US9002693B2Wire like link for cycle reproducible and cycle accurate hardware acceleratorASAAD SAMEH·Filed 2012·Granted Apr 7, 2015·7 cites·24 claims
- 0879US10176281B2Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware acceleratorIBM·Filed 2015·Granted Jan 8, 2019·2 cites·20 claims
- 0978US10904226B2Secure processing environment for protecting sensitive informationIBM·Filed 2019·Granted Jan 26, 2021·1 cites·20 claims
- 1074US10628579B2System and method for supporting secure objects using a memory access control monitorIBM·Filed 2015·Granted Apr 21, 2020·2 cites·10 claims
- 1172US8737233B2Increasing throughput of multiplexed electrical bus in pipe-lined architectureASAAD SAMEH·Filed 2011·Granted May 27, 2014·3 cites·15 claims
- 1271US9286423B2Cycle accurate and cycle reproducible memory for an FPGA based hardware acceleratorASAAD SAMEH W·Filed 2012·Granted Mar 15, 2016·2 cites·8 claims
- 1367US7724059B2Clock scaling circuitIBM·Filed 2004·Granted May 25, 2010·12 cites·21 claims
- 1466US8640070B2Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)ASAAD SAMEH W·Filed 2010·Granted Jan 28, 2014·3 cites·20 claims
- 1566US7757142B2Self-synchronizing pseudorandom bit sequence checkerIBM·Filed 2008·Granted Jul 13, 2010·2 cites·12 claims
- 1664US12061521B1Non-blocking hardware function request retries to address response latency variabilitiesIBM·Filed 2023·Granted Aug 13, 2024·0 cites·20 claims
- 1764US11047907B2Cycle accurate and cycle reproducible memory for an FPGA based hardware acceleratorIBM·Filed 2019·Granted Jun 29, 2021·0 cites·20 claims
- 1861US12287829B2Minimizing hash collisions of composite keysIBM·Filed 2023·Granted Apr 29, 2025·0 cites·20 claims
- 1961US10523640B2Secure processing environment for protecting sensitive informationIBM·Filed 2018·Granted Dec 31, 2019·0 cites·17 claims
- 2059US2021067256A1Transmit and receive radio frequency (rf) signals without the use of baseband generators and local oscillators for up conversion and down conversionIBM·Filed 2020·Application pending·0 cites
- 2156US7412640B2Self-synchronizing pseudorandom bit sequence checkerIBM·Filed 2003·Granted Aug 12, 2008·3 cites·5 claims
- 2256US2020272196A1Phase continuous signal generation using direct digital synthesisIBM·Filed 2020·Application pending·0 cites
- 2355US10488460B2Cycle accurate and cycle reproducible memory for an FPGA based hardware acceleratorIBM·Filed 2016·Granted Nov 26, 2019·0 cites·26 claims
- 2455US10158607B2Secure processing environment for protecting sensitive informationIBM·Filed 2015·Granted Dec 18, 2018·0 cites·13 claims
- 2553US10924193B2Transmit and receive radio frequency (RF) signals without the use of baseband generators and local oscillators for up conversion and down conversionIBM·Filed 2017·Granted Feb 16, 2021·0 cites·25 claims
- 2649US11907361B2System and method for supporting secure objects using a memory access control monitorIBM·Filed 2020·Granted Feb 20, 2024·0 cites·19 claims
- 2742US7177775B2Testable digital delay lineIBM·Filed 2005·Granted Feb 13, 2007·0 cites·7 claims
- 2842US2007038404A1Testable digital delay lineKAPUR MOHIT·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →