Inventor · disambiguated record
Moty Mehalel
Also filed as: MEHALEL MOTY
11 granted patents·1 pending application·126 citations·filing 1994–2013
90Inventor score
Top patents by PatentIndex Score
12 records- 0186US7424663B2Lowering voltage for cache memory operationINTEL CORP·Filed 2005·Granted Sep 9, 2008·19 cites·30 claims
- 0283US6256241B1Short write test mode for testing static memory cellsINTEL CORP·Filed 2000·Granted Jul 3, 2001·37 cites·19 claims
- 0376US8462541B2Circuits and methods for reducing minimum supply for register file cellsDE VIVEK·Filed 2012·Granted Jun 11, 2013·5 cites·18 claims
- 0473US6412038B1Integral modular cache for a processorINTEL CORP·Filed 2000·Granted Jun 25, 2002·21 cites·16 claims
- 0570US8824198B2Circuits and methods for reducing minimum supply for register file cellsINTEL CORP·Filed 2013·Granted Sep 2, 2014·3 cites·20 claims
- 0670US8111579B2Circuits and methods for reducing minimum supply for register file cellsDE VIVEK·Filed 2008·Granted Feb 7, 2012·6 cites·13 claims
- 0762US7590913B2Method and apparatus of reporting memory bit correctionINTEL CORP·Filed 2005·Granted Sep 15, 2009·2 cites·25 claims
- 0861US6885230B2Adaptive delay of timing control signalsINTEL CORP·Filed 2003·Granted Apr 26, 2005·8 cites·38 claims
- 0961US5475633ACache memory utilizing pseudo static four transistor memory cellINTEL CORP·Filed 1994·Granted Dec 12, 1995·22 cites·9 claims
- 1059US7877666B2Tracking health of integrated circuit structuresINTEL CORP·Filed 2006·Granted Jan 25, 2011·1 cites·33 claims
- 1155US7187224B2Adaptive delay of timing control signalsINTEL CORP·Filed 2005·Granted Mar 6, 2007·2 cites·19 claims
- 1243US2007043965A1Dynamic memory sizing for power reductionINTEL CORP·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →