Inventor · disambiguated record
Mustafa Badaroglu
Also filed as: BADAROGLU MUSTAFA
35 granted patents·26 pending applications·539 citations·filing 2001–2024
97Inventor score
Top patents by PatentIndex Score
61 records- 0198US10332881B1Integrating a gate-all-around (GAA) field-effect transistor(s) (FET(S)) and a finFET(s) on a common substrate of a semiconductor dieQUALCOMM INC·Filed 2018·Granted Jun 25, 2019·59 cites·17 claims
- 0297US9793164B2Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devicesQUALCOMM INC·Filed 2015·Granted Oct 17, 2017·23 cites·19 claims
- 0396US9871121B2Semiconductor device having a gap defined thereinQUALCOMM INC·Filed 2014·Granted Jan 16, 2018·25 cites·16 claims
- 0495US10109646B1Selectively recessing trench isolation in three-dimensional (3D) transistors to vary channel structure exposures from trench isolation to control drive strengthQUALCOMM INC·Filed 2017·Granted Oct 23, 2018·23 cites·36 claims
- 0595US9799560B2Self-aligned structureQUALCOMM INC·Filed 2015·Granted Oct 24, 2017·13 cites·40 claims
- 0693US8134358B2Method of auto calibrating a magnetic field sensor for drift and structure thereforCHARLIER OLIVIER·Filed 2007·Granted Mar 13, 2012·77 cites·9 claims
- 0792US9953979B2Contact wrap around structureQUALCOMM INC·Filed 2015·Granted Apr 24, 2018·8 cites·14 claims
- 0892US6941258B2Method, apparatus and computer program product for determination of noise in mixed signal systemsIMEC INTER UNI MICRO ELECTR·Filed 2001·Granted Sep 6, 2005·241 cites·32 claims
- 0991US10607896B2Method of forming gate of semiconductor device and semiconductor device having sameIMEC VZW·Filed 2017·Granted Mar 31, 2020·9 cites·17 claims
- 1091US9824936B2Adjacent device isolationQUALCOMM INC·Filed 2016·Granted Nov 21, 2017·6 cites·10 claims
- 1188US8773157B2Test circuit for testing through-silicon-vias in 3D integrated circuitsBADAROGLU MUSTAFA·Filed 2011·Granted Jul 8, 2014·12 cites·19 claims
- 1287US9502414B2Adjacent device isolationQUALCOMM INC·Filed 2015·Granted Nov 22, 2016·4 cites·18 claims
- 1385US10283526B2Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage dropQUALCOMM INC·Filed 2016·Granted May 7, 2019·5 cites·26 claims
- 1484US10157992B2Nanowire device with reduced parasiticsQUALCOMM INC·Filed 2015·Granted Dec 18, 2018·3 cites·7 claims
- 1584US10043796B2Vertically stacked nanowire field effect transistorsQUALCOMM INC·Filed 2016·Granted Aug 7, 2018·4 cites·33 claims
- 1684US9985014B2Minimum track standard cell circuits for reduced areaQUALCOMM INC·Filed 2016·Granted May 29, 2018·4 cites·26 claims
- 1783US12340304B2Partial sum management and reconfigurable systolic flow architectures for in-memory computationQUALCOMM INC·Filed 2021·Granted Jun 24, 2025·1 cites·13 claims
- 1883US9728718B2Magnetic tunnel junction (MTJ) device arrayQUALCOMM INC·Filed 2016·Granted Aug 8, 2017·3 cites·20 claims
- 1981US10032678B2Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devicesQUALCOMM INC·Filed 2016·Granted Jul 24, 2018·3 cites·29 claims
- 2077US2025124284A1Partial sum management and reconfigurable systolic flow architectures for in-memory computationQUALCOMM INC·Filed 2024·Application pending·0 cites
- 2176US9570509B2Magnetic tunnel junction (MTJ) device arrayQUALCOMM INC·Filed 2015·Granted Feb 14, 2017·2 cites·30 claims
- 2273US10090244B2Standard cell circuits employing high aspect ratio voltage rails for reduced resistanceQUALCOMM INC·Filed 2017·Granted Oct 2, 2018·2 cites·26 claims
- 2373US7987382B2Method and apparatus for minimizing the influence of a digital sub-circuit on at least partially digital circuitsIMEC·Filed 2006·Granted Jul 26, 2011·7 cites·38 claims
- 2472US10079293B2Semiconductor device having a gap defined thereinQUALCOMM INC·Filed 2017·Granted Sep 18, 2018·1 cites·23 claims
- 2566US12513915B2Dynamic random-access memory (DRAM) on hot compute logic for last-level-cacheQUALCOMM INC·Filed 2023·Granted Dec 30, 2025·0 cites·20 claims
- 2663US2025380406A1Vertical bank redundancy in three-dimensional stacked dynamic random-access memory (dram) for improved yieldQUALCOMM INC·Filed 2024·Application pending·0 cites
- 2763US2025380431A1High-bandwidth three-dimensional stacked memory with a base die enabling compute logic without memory power grid restrictionsQUALCOMM INC·Filed 2024·Application pending·0 cites
- 2862US2025391739A1Dual-liner through-silicon via (tsv) for power and signal transmissionQUALCOMM INC·Filed 2024·Application pending·0 cites
- 2962US2025336891A1Single hybrid system-on-chip (soc) die structure with high memory bandwidth and densityQUALCOMM INC·Filed 2024·Application pending·0 cites
- 3061US2025385222A1High-bandwidth integrated circuit packaging of memory and logicQUALCOMM INC·Filed 2024·Application pending·0 cites
- 3161US2025380430A1High-bandwidth 3d stacked memory with a base die enabling compute logic without memory power grid restrictionsQUALCOMM INC·Filed 2024·Application pending·0 cites
- 3261US2025379188A1High-bandwidth memory (hbm) package-on-package (pop) dynamic random-access memory (dram) with semiconductor pillarsQUALCOMM INC·Filed 2024·Application pending·0 cites
- 3361US2025385209A1Bumpless fan-out wafer-level integrated circuit package including memory and logicQUALCOMM INC·Filed 2024·Application pending·0 cites
- 3461US2025386517A1High bandwidth small form factor 3d integrated circuit package including memory and logicQUALCOMM INC·Filed 2024·Application pending·0 cites
- 3560US2025336757A1Concurrent general-purpose memory die and near-memory compute die in system-in-package (sip)QUALCOMM INC·Filed 2024·Application pending·0 cites
- 3659US12019905B2Digital compute in memoryQUALCOMM INC·Filed 2022·Granted Jun 25, 2024·0 cites·23 claims
- 3758US9564518B2Method and apparatus for source-drain junction formation in a FinFET with in-situ dopingQUALCOMM INC·Filed 2014·Granted Feb 7, 2017·0 cites·17 claims
- 3857US9349686B2Reduced height M1 metal lines for local on-chip routingQUALCOMM INC·Filed 2014·Granted May 24, 2016·0 cites·20 claims
- 3957US2025087640A1Low energy and small form factor packageQUALCOMM INC·Filed 2023·Application pending·0 cites
- 4056US2025015047A1Single-step via-last process for multi-stack wafersQUALCOMM INC·Filed 2023·Application pending·0 cites
- 4155US12074109B2Trench power rail in cell circuits to reduce resistance and related power distribution networks and fabrication methodsQUALCOMM INC·Filed 2022·Granted Aug 27, 2024·0 cites·19 claims
- 4255US2024282729A1Package dies including vertical interconnects for signal and power distribution in a three-dimensional (3d) integrated circuit (ic) packageQUALCOMM INC·Filed 2023·Application pending·0 cites
- 4354US7885326B2Method for determining a pulse position in a signalIMEC·Filed 2007·Granted Feb 8, 2011·2 cites·12 claims
- 4454US2019067435A1Nanowire device with reduced parasiticsQUALCOMM INC·Filed 2018·Application pending·0 cites
- 4552US9666481B2Reduced height M1 metal lines for local on-chip routingQUALCOMM INC·Filed 2016·Granted May 30, 2017·0 cites·5 claims
- 4650US8233579B2Devices comprising delay line for applying variable delay to clock signalBADAROGLU MUSTAFA·Filed 2007·Granted Jul 31, 2012·2 cites·15 claims
- 4750US2023025068A1Hybrid machine learning architecture with neural processing unit and compute-in-memory processing elementsQUALCOMM INC·Filed 2022·Application pending·0 cites
- 4849US11121075B2Hybrid metallization interconnects for power distribution and signalingQUALCOMM INC·Filed 2018·Granted Sep 14, 2021·0 cites·14 claims
- 4949US2017104088A1Method and apparatus for source-drain junction formation in a finfet with in-situ dopingQUALCOMM INC·Filed 2016·Application pending·0 cites
- 5048US9496181B2Sub-fin device isolationQUALCOMM INC·Filed 2014·Granted Nov 15, 2016·0 cites·12 claims
Showing the top 50 of 61 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →