Inventor · disambiguated record
Mutsunori Igarashi
Also filed as: IGARASHI MUTSUNORI
22 granted patents·1 pending application·1,752 citations·filing 1992–2006
97Inventor score
Files withTOSHIBA KK22
Top patents by PatentIndex Score
23 records- 0198US6792593B2Pattern correction method, apparatus, and programTOSHIBA KK·Filed 2002·Granted Sep 14, 2004·225 cites·17 claims
- 0298US6262487B1Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging methodTOSHIBA KK·Filed 1999·Granted Jul 17, 2001·452 cites·15 claims
- 0397US6645842B2Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging methodTOSHIBA KK·Filed 2002·Granted Nov 11, 2003·125 cites·22 claims
- 0497US6546540B1Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design programTOSHIBA KK·Filed 2000·Granted Apr 8, 2003·157 cites·11 claims
- 0597US6436804B2Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging methodTOSHIBA KK·Filed 2001·Granted Aug 20, 2002·138 cites·10 claims
- 0692US5224057AArrangement method for logic cells in semiconductor IC deviceTOSHIBA KK·Filed 1992·Granted Jun 29, 1993·304 cites·4 claims
- 0789US7539952B2Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuitTOSHIBA KK·Filed 2006·Granted May 26, 2009·9 cites·6 claims
- 0888US6813756B2Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design programTOSHIBA KK·Filed 2002·Granted Nov 2, 2004·46 cites·19 claims
- 0987US6779167B2Automated wiring pattern layout methodTOSHIBA KK·Filed 2002·Granted Aug 17, 2004·44 cites·7 claims
- 1083US6763508B2Layout design system, layout design method and layout design program of semiconductor integrated circuit, and method of manufacturing the sameTOSHIBA KK·Filed 2002·Granted Jul 13, 2004·30 cites·7 claims
- 1180US5397749AMethod for arranging logical cells in a semiconductor integrated circuitTOSHIBA KK·Filed 1992·Granted Mar 14, 1995·47 cites·5 claims
- 1277US6459331B1Noise suppression circuit, ASIC, navigation apparatus communication circuit, and communication apparatus having the sameTOSHIBA KK·Filed 1998·Granted Oct 1, 2002·26 cites·5 claims
- 1376US6904572B2Method, apparatus and program for designing a semiconductor integrated circuit by adjusting loading of pathsTOSHIBA KK·Filed 2003·Granted Jun 7, 2005·23 cites·17 claims
- 1473US7127694B2Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuitTOSHIBA KK·Filed 2004·Granted Oct 24, 2006·10 cites·4 claims
- 1570US7013444B2Layout design system, layout design method and layout design program of semiconductor integrated circuit, and method of manufacturing the sameTOSHIBA KK·Filed 2004·Granted Mar 14, 2006·12 cites·8 claims
- 1667US5801960ALayout method of wiring pattern for semiconductor integrated circuitTOSHIBA KK·Filed 1997·Granted Sep 1, 1998·53 cites·18 claims
- 1760US7124389B2Automated wiring pattern layout methodTOSHIBA KK·Filed 2004·Granted Oct 17, 2006·8 cites·2 claims
- 1858US5986961ASemiconductor integrated circuit of low power consumption typeTOSHIBA KK·Filed 1997·Granted Nov 16, 1999·17 cites·12 claims
- 1957US7064691B2Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the sameTOSHIBA KK·Filed 2002·Granted Jun 20, 2006·6 cites·3 claims
- 2051US7230554B2Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the sameTOSHIBA KK·Filed 2006·Granted Jun 12, 2007·1 cites·3 claims
- 2151US6097043ASemiconductor integrated circuit and supply method for supplying multiple supply voltages in a semiconductor integrated circuitTOSHIBA KK·Filed 1997·Granted Aug 1, 2000·17 cites·7 claims
- 2245US6683336B1Semiconductor integrated circuit, supply method for supplying multiple supply voltages in semiconductor integrated circuit, and record medium for storing program of supply method for supplying multiple supply voltages in semiconductor integrated circuitTOSHIBA KK·Filed 2000·Granted Jan 27, 2004·2 cites·2 claims
- 2345US2004237060A1Integrated circuit device, clock layout system, clock layout method, and clock layout programFiled 2004·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Mutsunori Igarashi files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →