Inventor · disambiguated record
Narasipur G. Anantha
Also filed as: ANANTHA NARASIPUR G · ANANTHA NARASIPUR GUNDAPPA
24 granted patents·699 citations·filing 1975–1987
97Inventor score
Files withIBM24
Top patents by PatentIndex Score
24 records- 0190US4139910ACharge coupled device memory with method of doubled storage capacity and independent of process parameters and temperatureIBM·Filed 1976·Granted Feb 13, 1979·42 cites·9 claims
- 0285US4264382AMethod for making a lateral PNP or NPN with a high gain utilizing reactive ion etching of buried high conductivity regionsIBM·Filed 1979·Granted Apr 28, 1981·51 cites·11 claims
- 0385US4160991AHigh performance bipolar device and method for making sameIBM·Filed 1977·Granted Jul 10, 1979·45 cites·8 claims
- 0484US4252582ASelf aligned method for making bipolar transistor having minimum base to emitter contact spacingIBM·Filed 1980·Granted Feb 24, 1981·58 cites·11 claims
- 0583US4691435AMethod for making Schottky diode having limited area self-aligned guard ringIBM·Filed 1981·Granted Sep 8, 1987·35 cites·13 claims
- 0678US4546536AFabrication methods for high performance lateral bipolar transistorsIBM·Filed 1983·Granted Oct 15, 1985·42 cites·15 claims
- 0778US4427989AHigh density memory cellIBM·Filed 1981·Granted Jan 24, 1984·29 cites·10 claims
- 0877US4236294AHigh performance bipolar device and method for making sameIBM·Filed 1979·Granted Dec 2, 1980·31 cites·11 claims
- 0974US4228369AIntegrated circuit interconnection structure having precision terminating resistorsIBM·Filed 1977·Granted Oct 14, 1980·32 cites·11 claims
- 1073US4510676AMethod of fabricating a lateral PNP transistorIBM·Filed 1983·Granted Apr 16, 1985·26 cites·4 claims
- 1173US4228450ABuried high sheet resistance structure for high density integrated circuits with reach through contactsIBM·Filed 1977·Granted Oct 14, 1980·30 cites·12 claims
- 1271US4583106AFabrication methods for high performance lateral bipolar transistorsIBM·Filed 1985·Granted Apr 15, 1986·39 cites·14 claims
- 1371US4159915AMethod for fabrication vertical NPN and PNP structures utilizing ion-implantationIBM·Filed 1977·Granted Jul 3, 1979·28 cites·14 claims
- 1470US4492008AMethods for making high performance lateral bipolar transistorsIBM·Filed 1983·Granted Jan 8, 1985·31 cites·13 claims
- 1570US4389281AMethod of planarizing silicon dioxide in semiconductor devicesIBM·Filed 1980·Granted Jun 21, 1983·32 cites·6 claims
- 1668US4269631ASelective epitaxy method using laser annealing for making filamentary transistorsIBM·Filed 1980·Granted May 26, 1981·30 cites·11 claims
- 1768US4214315AMethod for fabricating vertical NPN and PNP structures and the resulting productIBM·Filed 1979·Granted Jul 22, 1980·25 cites·12 claims
- 1866US4196440ALateral PNP or NPN with a high gainIBM·Filed 1978·Granted Apr 1, 1980·23 cites·10 claims
- 1962US4252581ASelective epitaxy method for making filamentary pedestal transistorIBM·Filed 1979·Granted Feb 24, 1981·19 cites·5 claims
- 2056US4117546AInterlaced ccd memoryIBM·Filed 1977·Granted Sep 26, 1978·10 cites·12 claims
- 2155US4010482ANon-volatile schottky barrier diode memory cellIBM·Filed 1975·Granted Mar 1, 1977·9 cites·5 claims
- 2253US4389294AMethod for avoiding residue on a vertical walled mesaIBM·Filed 1981·Granted Jun 21, 1983·17 cites·7 claims
- 2346US4796069ASchottky diode having limited area self-aligned guard ring and method for making sameIBM·Filed 1987·Granted Jan 3, 1989·10 cites·2 claims
- 2434US4316319AMethod for making a high sheet resistance structure for high density integrated circuitsIBM·Filed 1980·Granted Feb 23, 1982·5 cites·7 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →