Inventor · disambiguated record
Nagabhushan Chitlur
Also filed as: CHITLUR NAGABHUSHAN
16 granted patents·19 pending applications·36 citations·filing 2005–2024
90Inventor score
Top patents by PatentIndex Score
35 records- 0187US12204441B2Flushing cache lines involving persistent memoryINTEL CORP·Filed 2020·Granted Jan 21, 2025·2 cites·18 claims
- 0285US11194753B2Platform interface layer and protocol for acceleratorsINTEL CORP·Filed 2017·Granted Dec 7, 2021·4 cites·24 claims
- 0381US9329900B2Hetergeneous processor apparatus and methodINTEL CORP·Filed 2012·Granted May 3, 2016·6 cites·25 claims
- 0479US8082418B2Method and apparatus for coherent device initialization and accessSTILLWELL JR PAUL M·Filed 2007·Granted Dec 20, 2011·10 cites·16 claims
- 0574US2025117319A1Flushing Cache Lines Involving Persistent MemoryALTERA CORP·Filed 2024·Application pending·0 cites
- 0672US7617363B2Low latency message passing mechanismINTEL CORP·Filed 2005·Granted Nov 10, 2009·5 cites·20 claims
- 0770US11416300B2Modular accelerator function unit (AFU) design, discovery, and reuseINTEL CORP·Filed 2017·Granted Aug 16, 2022·1 cites·20 claims
- 0870US11251576B2Circuit card with coherent interconnectINTEL CORP·Filed 2018·Granted Feb 15, 2022·2 cites·8 claims
- 0969US12112204B2Modular accelerator function unit (AFU) design, discovery, and reuseINTEL CORP·Filed 2022·Granted Oct 8, 2024·0 cites·6 claims
- 1069US9639372B2Apparatus and method for heterogeneous processors mapping to virtual coresINTEL CORP·Filed 2012·Granted May 2, 2017·2 cites·22 claims
- 1166US8473715B2Dynamic accelerator reconfiguration via compiler-inserted initialization message and configuration address and size informationSTILLWELL JR PAUL M·Filed 2011·Granted Jun 25, 2013·2 cites·12 claims
- 1261US10019390B2Using memory cache for a race free interrupt scheme without the use of “read clear” registersCHITLUR NAGABHUSHAN·Filed 2012·Granted Jul 10, 2018·2 cites·21 claims
- 1355US12450008B2Remote storage for hardware microservices hosted on XPUs and SOC-XPU platformsINTEL CORP·Filed 2021·Granted Oct 21, 2025·0 cites·20 claims
- 1453US2024031457A1Programmable Device-Based Accelerator Framework for Virtualized EnvironmentsINTEL CORP·Filed 2023·Application pending·0 cites
- 1552US11372787B2Unified address space for multiple linksINTEL CORP·Filed 2017·Granted Jun 28, 2022·0 cites·26 claims
- 1652US2024037038A1Coherency Domain Cacheline State TrackingINTEL CORP·Filed 2023·Application pending·0 cites
- 1750US2023325265A1Hardware acceleration in a network interface deviceBALLE SUSANNE M·Filed 2023·Application pending·0 cites
- 1849US2023023229A1Volatile memory data recovery based on independent processing unit data accessINTEL CORP·Filed 2022·Application pending·0 cites
- 1949US2023344894A1Packet based in-line processing for data center environmentsINTEL CORP·Filed 2023·Application pending·0 cites
- 2048US10929134B2Execution unit acceleratorINTEL CORP·Filed 2019·Granted Feb 23, 2021·0 cites·16 claims
- 2148US2022269433A1System, method and apparatus for peer-to-peer communicationPAL RAHUL·Filed 2022·Application pending·0 cites
- 2248US2022321491A1Microservice data path and control path processingINTEL CORP·Filed 2022·Application pending·0 cites
- 2347US2022321434A1Method and apparatus to store and process telemetry data in a network device in a data centerINTEL CORP·Filed 2022·Application pending·0 cites
- 2447US2022206864A1Workload execution based on device characteristicsINTEL CORP·Filed 2022·Application pending·0 cites
- 2546US2023185760A1Technologies for hardware microservices accelerated in xpuINTEL CORP·Filed 2021·Application pending·0 cites
- 2645US2025156356A1Techniques to utilize near memory compute circuitry for memory-bound workloadsINTEL CORP·Filed 2022·Application pending·0 cites
- 2744US11809899B2Methods and apparatus for accelerating virtual machine migrationINTEL CORP·Filed 2019·Granted Nov 7, 2023·0 cites·20 claims
- 2844US2014281276A1Method, apparatus, and system for low latency communicationMAROLIA PRATIK M·Filed 2013·Application pending·0 cites
- 2943US7930459B2Coherent input output deviceINTEL CORP·Filed 2007·Granted Apr 19, 2011·0 cites·5 claims
- 3042US2019042329A1System with programmable multi-context accelerator circuitryKAKAIYA UTKARSH Y·Filed 2018·Application pending·0 cites
- 3140US2009327564A1Method and apparatus of implementing control and status registers using coherent system memoryCHITLUR NAGABHUSHAN·Filed 2008·Application pending·0 cites
- 3239US2025310263A1Systems and Methods for Packet Processing in Programmable Logic DevicesCHITLUR NAGABHUSHAN·Filed 2024·Application pending·0 cites
- 3338US2009089475A1Low latency interface between device driver and network interface cardCHITLUR NAGABHUSHAN·Filed 2007·Application pending·0 cites
- 3438US2018331900A1Reconfigurable device managerINTEL CORP·Filed 2017·Application pending·0 cites
- 3537US2008052463A1Method and apparatus to implement cache-coherent network interfacesCHITLUR NAGABHUSHAN·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →