Inventor · disambiguated record
Navneet Dour
Also filed as: DOUR NAVNEET
17 granted patents·3 pending applications·283 citations·filing 1999–2024
94Inventor score
Top patents by PatentIndex Score
20 records- 0196US7432731B2Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variationsINTEL CORP·Filed 2005·Granted Oct 7, 2008·67 cites·14 claims
- 0296US6563337B2Driver impedance control mechanismINTEL CORP·Filed 2001·Granted May 13, 2003·95 cites·25 claims
- 0389US7602859B2Calibrating integrating receivers for source synchronous protocolINTEL CORP·Filed 2005·Granted Oct 13, 2009·22 cites·27 claims
- 0488US11722128B2Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL)INTEL CORP·Filed 2021·Granted Aug 8, 2023·2 cites·20 claims
- 0588US7020818B2Method and apparatus for PVT controller for programmable on die terminationINTEL CORP·Filed 2004·Granted Mar 28, 2006·30 cites·9 claims
- 0683US11070200B2Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL)INTEL CORP·Filed 2018·Granted Jul 20, 2021·4 cites·25 claims
- 0774US6617891B2Slew rate at buffers by isolating predriver from driverINTEL CORP·Filed 2001·Granted Sep 9, 2003·15 cites·15 claims
- 0871US10613955B2Platform debug and testing with secured hardwareINTEL CORP·Filed 2017·Granted Apr 7, 2020·1 cites·20 claims
- 0966US7403034B2PVT controller for programmable on die terminationINTEL CORP·Filed 2006·Granted Jul 22, 2008·4 cites·11 claims
- 1062US7751274B2Extended synchronized clockINTEL CORP·Filed 2006·Granted Jul 6, 2010·2 cites·18 claims
- 1159US7746135B2Wake-up circuitINTEL CORP·Filed 2007·Granted Jun 29, 2010·4 cites·10 claims
- 1258US7012451B2Slew rate at buffers by isolating predriver from driverINTEL CORP·Filed 2003·Granted Mar 14, 2006·7 cites·15 claims
- 1358US6236250B1Circuit for independent power-up sequencing of a multi-voltage chipINTEL CORP·Filed 1999·Granted May 22, 2001·15 cites·14 claims
- 1455US7307900B2Method and apparatus for optimizing strobe to clock relationshipINTEL CORP·Filed 2004·Granted Dec 11, 2007·8 cites·12 claims
- 1554US2025385676A1Ultra-wide band ac-coupled bufferINTEL CORP·Filed 2024·Application pending·0 cites
- 1651US11042315B2Dynamically programmable memory test traffic routerINTEL CORP·Filed 2018·Granted Jun 22, 2021·0 cites·22 claims
- 1743US6414539B1AC timings at the input buffer of source synchronous and common clock designs by making the supply for differential amplifier track the reference voltageINTEL CORP·Filed 2001·Granted Jul 2, 2002·4 cites·15 claims
- 1841US7009894B2Dynamically activated memory controller data terminationINTEL CORP·Filed 2004·Granted Mar 7, 2006·3 cites·39 claims
- 1940US2006002482A1Signal drive de-emphasis for memory busWALKER CLINTON·Filed 2004·Application pending·0 cites
- 2039US2006245473A1Integrating receivers for source synchronous protocolCHENG ROGER K·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →