Inventor · disambiguated record
Nathan A. Eckel
Also filed as: ECKEL NATHAN A
21 granted patents·5 pending applications·160 citations·filing 2002–2024
94Inventor score
Top patents by PatentIndex Score
26 records- 0186US9171597B2Apparatuses and methods for providing strobe signals to memoriesMICRON TECHNOLOGY INC·Filed 2013·Granted Oct 27, 2015·8 cites·26 claims
- 0285US11070375B2Key encryption handlingMICRON TECHNOLOGY INC·Filed 2018·Granted Jul 20, 2021·4 cites·19 claims
- 0382US9437263B2Apparatuses and methods for providing strobe signals to memoriesMICRON TECHNOLOGY INC·Filed 2015·Granted Sep 6, 2016·3 cites·15 claims
- 0481US10642695B2Storage backed memory package save triggerMICRON TECHNOLOGY INC·Filed 2018·Granted May 5, 2020·2 cites·15 claims
- 0580US7739451B1Method and apparatus for stacked address, bus to memory data transferUNISYS CORP·Filed 2002·Granted Jun 15, 2010·34 cites·12 claims
- 0680US6996645B1Method and apparatus for spawning multiple requests from a single entry of a queueUNISYS CORP·Filed 2002·Granted Feb 7, 2006·30 cites·13 claims
- 0779US11074131B2Storage backed memory package save triggerMICRON TECHNOLOGY INC·Filed 2020·Granted Jul 27, 2021·1 cites·15 claims
- 0879US7051131B1Method and apparatus for recording and monitoring bus activity in a multi-processor environmentUNISYS CORP·Filed 2002·Granted May 23, 2006·36 cites·25 claims
- 0978US12443354B2Boot and initialization techniques for stacked memory architecturesMICRON TECHNOLOGY INC·Filed 2024·Granted Oct 14, 2025·0 cites·20 claims
- 1074US2025023727A1Key encryption handlingLODESTAR LICENSING GROUP LLC·Filed 2024·Application pending·0 cites
- 1173US7003628B1Buffered transfer of data blocks between memory and processors independent of the order of allocation of locations in the bufferUNISYS CORP·Filed 2002·Granted Feb 21, 2006·22 cites·17 claims
- 1272US10831393B2Partial save of memoryMICRON TECHNOLOGY INC·Filed 2018·Granted Nov 10, 2020·1 cites·19 claims
- 1370US11579979B2Storage backed memory package save triggerMICRON TECHNOLOGY INC·Filed 2021·Granted Feb 14, 2023·0 cites·15 claims
- 1470US10984881B1Memory sub-system self-testing operationsMICRON TECHNOLOGY INC·Filed 2019·Granted Apr 20, 2021·2 cites·15 claims
- 1569US12511192B2Information broadcast techniques for stacked memory architecturesMICRON TECHNOLOGY INC·Filed 2024·Granted Dec 30, 2025·0 cites·20 claims
- 1665US12137162B2Key encryption handlingLODESTAR LICENSING GROUP LLC·Filed 2021·Granted Nov 5, 2024·0 cites·18 claims
- 1764US7421545B1Method and apparatus for multiple sequence access to single entry queueUNISYS CORP·Filed 2002·Granted Sep 2, 2008·11 cites·13 claims
- 1863US7827455B1System and method for detecting glitches on a high-speed interfaceUNISYS CORP·Filed 2007·Granted Nov 2, 2010·4 cites·17 claims
- 1961US2025279133A2Interface techniques for stacked memory architecturesMICRON TECHNOLOGY INC·Filed 2024·Application pending·0 cites
- 2060US11579791B2Partial save of memoryMICRON TECHNOLOGY INC·Filed 2020·Granted Feb 14, 2023·0 cites·18 claims
- 2159US11514995B2Memory sub-system self-testing operationsMICRON TECHNOLOGY INC·Filed 2021·Granted Nov 29, 2022·0 cites·18 claims
- 2258US2025278481A2Row hammer mitigation for stacked memory architecturesMICRON TECHNOLOGY INC·Filed 2024·Application pending·0 cites
- 2357US2025278482A2Hammer mitigation reliability in stacked memory architecturesMICRON TECHNOLOGY INC·Filed 2024·Application pending·0 cites
- 2457US2025370621A2Interface layout for stacked memory architecturesMICRON TECHNOLOGY INC·Filed 2024·Application pending·0 cites
- 2552US7797472B2Method and apparatus for providing overlapping defer phase responsesUNISYS CORP·Filed 2004·Granted Sep 14, 2010·2 cites·20 claims
- 2640US11650925B2Memory interface managementMICRON TECHNOLOGY INC·Filed 2019·Granted May 16, 2023·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →