Inventor · disambiguated record
Narayanan Ramanan
Also filed as: RAMANAN NARAYANAN
9 granted patents·6 pending applications·6 citations·filing 2019–2025
77Inventor score
Top patents by PatentIndex Score
15 records- 0191US11094386B1Device, system, and method to verify data programming of a multi-level cell memory based on one of temperature, pressure, wear condition or relative position of the memory cellINTEL CORP·Filed 2020·Granted Aug 17, 2021·6 cites·20 claims
- 0283US2025364059A1Flash memory having improved performance as a consequence of program direction along a flash storage cell columnIntel NDTM US LLC·Filed 2025·Application pending·0 cites
- 0368US12051469B2Method and apparatus to mitigate hot electron read disturbs in 3D nand devicesIntel NDTM US LLC·Filed 2022·Granted Jul 30, 2024·0 cites·18 claims
- 0466US2024363173A1Modulation of source voltage in nand-flash array readIntel NDTM US LLC·Filed 2024·Application pending·0 cites
- 0561US12087365B2Modulation of source voltage in NAND-flash array readINTEL CORP·Filed 2021·Granted Sep 10, 2024·0 cites·20 claims
- 0661US2025384939A1Suspending within program-verify operations for shorter wait time to suspendMICRON TECHNOLOGY INC·Filed 2025·Application pending·0 cites
- 0761US2025364062A1Program suspend-resume operations in a memory deviceMICRON TECHNOLOGY INC·Filed 2025·Application pending·0 cites
- 0859US11355199B2Method and apparatus to mitigate hot electron read disturbs in 3D NAND devicesINTEL CORP·Filed 2020·Granted Jun 7, 2022·0 cites·20 claims
- 0955US2022084606A1Flash memory having improved performance as a consequence of program direction along a flash storage cell columnINTEL CORP·Filed 2020·Application pending·0 cites
- 1052US12266406B2NAND sensing circuit and technique for read-disturb mitigationINTEL CORP·Filed 2021·Granted Apr 1, 2025·0 cites·20 claims
- 1148US12322455B2Program verify process having placement aware pre-program verify (PPV) bucket size modulationIntel NDTM US LLC·Filed 2021·Granted Jun 3, 2025·0 cites·20 claims
- 1248US2024395344A1Mitigation of charge-loss in suspended program state in a memory deviceMICRON TECHNOLOGY INC·Filed 2024·Application pending·0 cites
- 1345US12394492B2Memory cell sensing circuit with adjusted bias from pre-boost operationIntel NDTM US LLC·Filed 2020·Granted Aug 19, 2025·0 cites·22 claims
- 1445US12237023B2Dynamic detection and dynamic adjustment of sub-threshold swing in a memory cell sensing circuitIntel NDTM US LLC·Filed 2020·Granted Feb 25, 2025·0 cites·21 claims
- 1545US10847234B2Program verify technique for non-volatile memoryINTEL CORP·Filed 2019·Granted Nov 24, 2020·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →