Inventor · disambiguated record
Natarajan Seshan
Also filed as: SESHAN NATARAJAN · SESHAN NATARAJAN NAT
18 granted patents·1,006 citations·filing 1996–2021
96Inventor score
Top patents by PatentIndex Score
18 records- 0197US11049586B2Systems and methods for implementing redundancy for tile-based intelligence processing computing architectureMYTHIC INC·Filed 2020·Granted Jun 29, 2021·8 cites·16 claims
- 0290US6182203B1MicroprocessorTEXAS INSTRUMENTS INC·Filed 1998·Granted Jan 30, 2001·181 cites·14 claims
- 0385US6112298AMethod for managing an instruction execution pipeline during debugging of a data processing systemTEXAS INSTRUMENTS INC·Filed 1997·Granted Aug 29, 2000·130 cites·24 claims
- 0484US6055649AProcessor test port with scan chains and data streamingTEXAS INSTRUMENTS INC·Filed 1997·Granted Apr 25, 2000·117 cites·20 claims
- 0578US6065106AResuming normal execution by restoring without refetching instructions in multi-word instruction register interrupted by debug instructions loading and processingTEXAS INSTRUMENTS INC·Filed 1997·Granted May 16, 2000·85 cites·22 claims
- 0677US6889320B1Microprocessor with an instruction immediately next to a branch instruction for adding a constant to a program counterTEXAS INSTRUMENTS INC·Filed 2000·Granted May 3, 2005·25 cites·21 claims
- 0776US6016555ANon-intrusive software breakpoints in a processor instruction execution pipelineTEXAS INSTRUMENTS INC·Filed 1997·Granted Jan 18, 2000·78 cites·20 claims
- 0876US5970241AMaintaining synchronism between a processor pipeline and subsystem pipelines during debugging of a data processing systemTEXAS INSTRUMENTS INC·Filed 1997·Granted Oct 19, 1999·78 cites·3 claims
- 0974US6081885AMethod and apparatus for halting a processor and providing state visibility on a pipeline phase basisTEXAS INSTRUMENTS INC·Filed 1997·Granted Jun 27, 2000·69 cites·15 claims
- 1067US6374346B1Processor with conditional execution of every instructionTEXAS INSTRUMENTS INC·Filed 1998·Granted Apr 16, 2002·50 cites·23 claims
- 1167US6058474AMethod and apparatus for DMA boot loading a microprocessor without an internal ROMTEXAS INSTRUMENTS INC·Filed 1998·Granted May 2, 2000·64 cites·23 claims
- 1266US11475973B2Systems and methods for implementing redundancy for tile-based intelligence processing computing architectureMYTHIC INC·Filed 2021·Granted Oct 18, 2022·0 cites·20 claims
- 1363US5958044AMulticycle NOPTEXAS INSTRUMENTS INC·Filed 1998·Granted Sep 28, 1999·46 cites·8 claims
- 1448US6055628AMicroprocessor with a nestable delayed branch instruction without branch related pipeline interlocksTEXAS INSTRUMENTS INC·Filed 1998·Granted Apr 25, 2000·21 cites·14 claims
- 1545US6351758B1Bit and digit reversal methodsTEXAS INSTRUMENTS INC·Filed 1999·Granted Feb 26, 2002·23 cites·4 claims
- 1643US6289443B1Self-priming loop execution for loop prolog instructionTEXAS INSTRUMENTS INC·Filed 1999·Granted Sep 11, 2001·15 cites·12 claims
- 1743US5841379AMethod and apparatus for selectively counting consecutive bitsTEXAS INSTRUMENTS INC·Filed 1997·Granted Nov 24, 1998·10 cites·1 claims
- 1836US5862159AParallelized cyclical redundancy check methodTEXAS INSTRUMENTS INC·Filed 1996·Granted Jan 19, 1999·6 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →