Inventor · disambiguated record
Nalini Vasudevan
Also filed as: VASUDEVAN NALINI
15 granted patents·6 pending applications·37 citations·filing 2010–2017
90Inventor score
Technology areasG06F
Top patents by PatentIndex Score
21 records- 0187US9244677B2Loop vectorization methods and apparatusINTEL CORP·Filed 2012·Granted Jan 26, 2016·9 cites·15 claims
- 0283US9733913B2Methods and systems to vectorize scalar computer program loops having loop-carried dependencesINTEL CORP·Filed 2016·Granted Aug 15, 2017·3 cites·14 claims
- 0382US9898266B2Loop vectorization methods and apparatusINTEL CORP·Filed 2016·Granted Feb 20, 2018·3 cites·20 claims
- 0481US10402177B2Methods and systems to vectorize scalar computer program loops having loop-carried dependencesINTEL CORP·Filed 2017·Granted Sep 3, 2019·2 cites·29 claims
- 0579US9268541B2Methods and systems to vectorize scalar computer program loops having loop-carried dependencesINTEL CORP·Filed 2013·Granted Feb 23, 2016·4 cites·16 claims
- 0676US9921832B2Instruction to reduce elements in a vector register with strided access patternINTEL CORP·Filed 2012·Granted Mar 20, 2018·4 cites·17 claims
- 0776US9798541B2Apparatus and method for propagating conditionally evaluated values in SIMD/vector execution using an input mask registerBHARADWAJ JAYASHANKAR·Filed 2011·Granted Oct 24, 2017·4 cites·23 claims
- 0873US9703558B2Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediateLEE VICTOR W·Filed 2011·Granted Jul 11, 2017·3 cites·14 claims
- 0971US9690582B2Instruction and logic for cache-based speculative vectorizationVASUDEVAN NALINI·Filed 2013·Granted Jun 27, 2017·4 cites·20 claims
- 1065US9710279B2Method and apparatus for speculative vectorizationINTEL CORP·Filed 2014·Granted Jul 18, 2017·1 cites·22 claims
- 1157US10372450B2Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediateINTEL CORP·Filed 2017·Granted Aug 6, 2019·0 cites·20 claims
- 1253US2018004517A1Apparatus and method for propagating conditionally evaluated values in simd/vector execution using an input mask registerINTEL CORP·Filed 2017·Application pending·0 cites
- 1351US9910650B2Method and apparatus for approximating detection of overlaps between memory rangesINTEL CORP·Filed 2014·Granted Mar 6, 2018·0 cites·21 claims
- 1448US9720667B2Automatic loop vectorization using hardware transactional memoryINTEL CORP·Filed 2014·Granted Aug 1, 2017·0 cites·19 claims
- 1547US2018018177A1Method and apparatus for speculative vectorizationVASUDEVAN NALINI·Filed 2017·Application pending·0 cites
- 1646US9189236B2Speculative non-faulting loads and gathersBHARADWAJ JAYASHANKAR·Filed 2012·Granted Nov 17, 2015·0 cites·24 claims
- 1741US9268626B2Apparatus and method for vectorization with speculation supportBHARADWAJ JAYASHANKAR·Filed 2011·Granted Feb 23, 2016·0 cites·17 claims
- 1841US2013311530A1Apparatus and method for selecting elements of a vector computationLEE VICTOR W·Filed 2012·Application pending·0 cites
- 1940US2014089634A1Apparatus and method for detecting identical elements within a vector registerLEE VICTOR W·Filed 2011·Application pending·0 cites
- 2040US2013332701A1Apparatus and method for selecting elements of a vector computationBHARADWAJ JAYASHANKAR·Filed 2011·Application pending·0 cites
- 2135US2012054394A1Fast Biased LocksNAMJOSHI KEDAR S·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →