Inventor · disambiguated record
Narasimhan Vasudevan
Also filed as: VASUDEVAN NARASIMHAN
12 granted patents·2 pending applications·147 citations·filing 2000–2017
91Inventor score
Top patents by PatentIndex Score
14 records- 0195US7307468B1Bandgap system with tunable temperature coefficient of the output voltageXILINX INC·Filed 2006·Granted Dec 11, 2007·40 cites·16 claims
- 0293US7265605B1Supply regulator for memory cells with suspend mode capability for low power applicationsXILINX INC·Filed 2005·Granted Sep 4, 2007·30 cites·20 claims
- 0380US7701245B1Enhanced voltage regulation with power supply disable capability for low-power operationXILINX INC·Filed 2007·Granted Apr 20, 2010·11 cites·19 claims
- 0480US7321256B1Highly reliable and zero static current start-up circuitsXILINX INC·Filed 2005·Granted Jan 22, 2008·13 cites·15 claims
- 0578US7733075B1Voltage sensing in a supply regulator for a suspend modeXILINX INC·Filed 2007·Granted Jun 8, 2010·12 cites·20 claims
- 0677US7667489B1Power-on reset circuit for a voltage regulator having multiple power supply voltagesXILINX INC·Filed 2007·Granted Feb 23, 2010·9 cites·8 claims
- 0772US8120430B1Stable VCO operation in absence of clock signalVASUDEVAN NARASIMHAN·Filed 2009·Granted Feb 21, 2012·10 cites·20 claims
- 0871US6509739B1Method for locating defects and measuring resistance in a test structureXILINX INC·Filed 2000·Granted Jan 21, 2003·15 cites·20 claims
- 0969US10014866B2Clock alignment scheme for data macros of DDR PHYINVECAS INC·Filed 2017·Granted Jul 3, 2018·2 cites·19 claims
- 1063US7859936B1Method and apparatus for saving and restoring the state of a power-gated memory deviceXILINX INC·Filed 2009·Granted Dec 28, 2010·5 cites·20 claims
- 1144US2015108842A1Systems and methods for reducing cross-supply currentQUALCOMM INC·Filed 2013·Application pending·0 cites
- 1243US9954538B2Clock alignment scheme for data macros of DDR PHYINVECAS INC·Filed 2016·Granted Apr 24, 2018·0 cites·7 claims
- 1337US9213487B2Receiver architecture for memory readsQUALCOMM INC·Filed 2013·Granted Dec 15, 2015·0 cites·15 claims
- 1435US2015109034A1Delay architecture for reducing downtime during frequency switchingQUALCOMM INC·Filed 2013·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →