Inventor · disambiguated record
Nancy Zelick
Also filed as: ZELICK NANCY · ZELICK NANCY M
21 granted patents·12 pending applications·307 citations·filing 2004–2023
94Inventor score
Top patents by PatentIndex Score
33 records- 0197US8211772B2Two-dimensional condensation for uniaxially strained semiconductor finsKAVALIEROS JACK T·Filed 2009·Granted Jul 3, 2012·72 cites·20 claims
- 0297US7348284B2Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flowINTEL CORP·Filed 2004·Granted Mar 25, 2008·141 cites·10 claims
- 0393US8558279B2Non-planar device having uniaxially strained semiconductor body and method of making sameCEA STEPHEN M·Filed 2010·Granted Oct 15, 2013·15 cites·20 claims
- 0492US9029835B2Epitaxial film on nanoscale structureINTEL CORP·Filed 2012·Granted May 12, 2015·13 cites·19 claims
- 0592US7960794B2Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flowINTEL CORP·Filed 2007·Granted Jun 14, 2011·20 cites·10 claims
- 0690US8872225B2Defect transferred and lattice mismatched epitaxial filmINTEL CORP·Filed 2012·Granted Oct 28, 2014·12 cites·25 claims
- 0788US9391181B2Lattice mismatched hetero-epitaxial filmINTEL CORP·Filed 2012·Granted Jul 12, 2016·10 cites·14 claims
- 0886US9711598B2Two-dimensional condensation for uniaxially strained semiconductor finsINTEL CORP·Filed 2016·Granted Jul 18, 2017·3 cites·15 claims
- 0981US8334184B2Polish to remove topography in sacrificial gate layer prior to gate patterningSTEIGERWALD JOSEPH M·Filed 2009·Granted Dec 18, 2012·10 cites·17 claims
- 1080US10249490B2Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxyINTEL CORP·Filed 2017·Granted Apr 2, 2019·2 cites·20 claims
- 1179US9159835B2Two-dimensional condensation for uniaxially strained semiconductor finsKAVALIEROS JACK T·Filed 2012·Granted Oct 13, 2015·3 cites·19 claims
- 1278US11164974B2Channel layer formed in an art trenchINTEL CORP·Filed 2017·Granted Nov 2, 2021·2 cites·18 claims
- 1374US9640537B2Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxyINTEL CORP·Filed 2013·Granted May 2, 2017·2 cites·25 claims
- 1466US8878363B2Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing sameDEWEY GILBERT·Filed 2009·Granted Nov 4, 2014·2 cites·17 claims
- 1560US10304929B2Two-dimensional condensation for uniaxially strained semiconductor finsINTEL CORP·Filed 2017·Granted May 28, 2019·0 cites·12 claims
- 1659US2025212441A1Incorporation of semiconductor doping materials in metal contacts via reactive sputteringINTEL CORP·Filed 2023·Application pending·0 cites
- 1758US10756198B2Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing sameINTEL CORP·Filed 2017·Granted Aug 25, 2020·0 cites·11 claims
- 1857US9768269B2Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing sameINTEL CORP·Filed 2014·Granted Sep 19, 2017·0 cites·31 claims
- 1957US9419140B2Two-dimensional condensation for uniaxially strained semiconductor finsKAVALIEROS JACK T·Filed 2015·Granted Aug 16, 2016·0 cites·17 claims
- 2057US2025212507A1Cmos metal contacts with dopant diffusion barriersINTEL CORP·Filed 2023·Application pending·0 cites
- 2157US2025220958A1Source/drain contact trench with dielectric liner on contact metalINTEL CORP·Filed 2023·Application pending·0 cites
- 2253US9680013B2Non-planar device having uniaxially strained semiconductor body and method of making sameINTEL CORP·Filed 2013·Granted Jun 13, 2017·0 cites·17 claims
- 2352US9865684B2Nanoscale structure with epitaxial film having a recessed bottom portionINTEL CORP·Filed 2015·Granted Jan 9, 2018·0 cites·20 claims
- 2452US2024105508A1Integrated circuit devices with contacts using nitridized molybdenumINTEL CORP·Filed 2022·Application pending·0 cites
- 2552US2024006506A1Low-resistance and thermally stable contacts with phosphide or arsenide metal compound layersINTEL CORP·Filed 2022·Application pending·0 cites
- 2651US2024006488A1Capping source and drain regions of transistors to prevent diffusion of dopants during fabricationINTEL CORP·Filed 2022·Application pending·0 cites
- 2750US2024006494A1Source and drain refractory metal capINTEL CORP·Filed 2022·Application pending·0 cites
- 2850US2024006533A1Low-resistance and thermally stable contacts with boride, indium, or gallium metal compound layersINTEL CORP·Filed 2022·Application pending·0 cites
- 2947US11631737B2Ingaas epi structure and wet etch process for enabling III-v GAA in art trenchINTEL CORP·Filed 2014·Granted Apr 18, 2023·0 cites·16 claims
- 3046US2017317187A1Uniform Layers Formed with Aspect Ratio Trench Based ProcessesINTEL CORP·Filed 2014·Application pending·0 cites
- 3142US2016190319A1Non-Planar Semiconductor Devices having Multi-Layered Compliant SubstratesINTEL CORP·Filed 2013·Application pending·0 cites
- 3242US2017323963A1Thin channel region on wide subfinINTEL CORP·Filed 2014·Application pending·0 cites
- 3339US2007262399A1Sealing spacer to reduce or eliminate lateral oxidation of a high-k gate dielectricDEWEY GILBERT·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →