Inventor · disambiguated record
Nevine Nassif
Also filed as: NASSIF NEVINE
13 granted patents·1 pending application·79 citations·filing 1997–2023
89Inventor score
Top patents by PatentIndex Score
14 records- 0194US10795853B2Multiple dies hardware processors and methodsINTEL CORP·Filed 2017·Granted Oct 6, 2020·9 cites·24 claims
- 0291US11586579B2Multiple dies hardware processors and methodsINTEL CORP·Filed 2021·Granted Feb 21, 2023·2 cites·24 claims
- 0376US11899615B2Multiple dies hardware processors and methodsINTEL CORP·Filed 2023·Granted Feb 13, 2024·0 cites·24 claims
- 0467US6654713B1Method to compress a piecewise linear waveform so compression error occurs on only one side of the waveformHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Nov 25, 2003·29 cites·31 claims
- 0565US11294852B2Multiple dies hardware processors and methodsINTEL CORP·Filed 2020·Granted Apr 5, 2022·0 cites·25 claims
- 0657US2021375825A1Functionally redundant semiconductor dies and packageINTEL CORP·Filed 2021·Application pending·0 cites
- 0752US12469820B2Fine-grained disaggregated server architectureINTEL CORP·Filed 2021·Granted Nov 11, 2025·0 cites·20 claims
- 0848US11127712B2Functionally redundant semiconductor dies and packageINTEL CORP·Filed 2017·Granted Sep 21, 2021·0 cites·16 claims
- 0946US6046984APruning of short paths in static timing verifierDIGITAL EQUIPMENT CORP·Filed 1997·Granted Apr 4, 2000·21 cites·21 claims
- 1042US6877142B2Timing verifier for MOS devices and related methodHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Apr 5, 2005·0 cites·18 claims
- 1133US6606587B1Method and apparatus for estimating elmore delays within circuit designsHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Aug 12, 2003·10 cites·16 claims
- 1229US6473888B1Timing verifier for MOS devices and related methodCOMPAQ COMPUTER CORP·Filed 1998·Granted Oct 29, 2002·4 cites·10 claims
- 1326US6658506B1Method and apparatus for performing timing verification of a circuitCOMPAQ COMPUTER CORP·Filed 1999·Granted Dec 2, 2003·4 cites·13 claims
- 1425US6438732B1Method and apparatus for modeling gate capacitance of symmetrically and asymmetrically sized differential cascode voltage swing logic (DCVSL)COMPAQ COMPUTER CORP·Filed 1999·Granted Aug 20, 2002·0 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →