Inventor · disambiguated record
Neha Srivastava
Also filed as: SRIVASTAVA NEHA
13 granted patents·7 pending applications·20 citations·filing 2009–2025
84Inventor score
Top patents by PatentIndex Score
20 records- 0195US11018657B1Clock glitch alerting circuitNXP USA INC·Filed 2020·Granted May 25, 2021·9 cites·20 claims
- 0289US11175340B1System and method for managing testing and availability of critical components on system-on-chipNXP BV·Filed 2021·Granted Nov 16, 2021·2 cites·20 claims
- 0377US7808279B2Low power, self-gated, pulse triggered clock gating cellFREESCALE SEMICONDUCTOR INC·Filed 2009·Granted Oct 5, 2010·9 cites·12 claims
- 0466US12259764B2Architecture for managing asynchronous resets in a system-on-a-chipNXP USA INC·Filed 2023·Granted Mar 25, 2025·0 cites·19 claims
- 0555US2025182100A1Systems and methods for enterprise-wide tokenization of payment card industry dataJPMORGAN CHASE BANK NA·Filed 2024·Application pending·0 cites
- 0655US2025216454A1Configurable multilayered override system and method for circumventing semiconductor circuitry with unpredictable silicon behaviorNXP BV·Filed 2024·Application pending·0 cites
- 0751US11797373B2System and method for managing faults in integrated circuitsNXP BV·Filed 2021·Granted Oct 24, 2023·0 cites·20 claims
- 0851US11520653B2System and method for controlling faults in system-on-chipNXP USA INC·Filed 2020·Granted Dec 6, 2022·0 cites·18 claims
- 0950US11609821B2Method and system for managing fault recovery in system-on-chipsNXP USA INC·Filed 2020·Granted Mar 21, 2023·0 cites·23 claims
- 1050US11422185B2System and method for testing critical components on system-on-chipNXP USA INC·Filed 2020·Granted Aug 23, 2022·0 cites·20 claims
- 1149US12105583B2Fault recovery system for functional circuitsNXP BV·Filed 2022·Granted Oct 1, 2024·0 cites·19 claims
- 1248US2025184328A1Systems and methods for restricting access to tokenization servicesJPMORGAN CHASE BANK NA·Filed 2024·Application pending·0 cites
- 1348US2025299181A1Systems and methods for token versioning and reissueJPMORGAN CHASE BANK NA·Filed 2025·Application pending·0 cites
- 1446US12124347B2System and method for managing secure memories in integrated circuitsNXP BV·Filed 2023·Granted Oct 22, 2024·0 cites·20 claims
- 1546US2024353479A1On-chip fault detection due to malfunctions on chip pinsNXP USA INC·Filed 2023·Application pending·0 cites
- 1642US11482992B2Clock sweeping systemNXP USA INC·Filed 2020·Granted Oct 25, 2022·0 cites·20 claims
- 1741US2024160745A1Testing of security systems in integrated circuitsNXP BV·Filed 2023·Application pending·0 cites
- 1837US11550684B2Testing of lockstep architecture in system-on-chipsNXP BV·Filed 2021·Granted Jan 10, 2023·0 cites·20 claims
- 1932US9891654B2Secure clock switch circuitFREESCALE SEMICONDUCTOR INC·Filed 2016·Granted Feb 13, 2018·0 cites·13 claims
- 2032US2011181331A1Integrated circuit with leakage reduction in static netsFREESCALE SEMICONDUCTOR INC·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →