Inventor · disambiguated record
Nelson Wu
Also filed as: WU NELSON
15 granted patents·10 citations·filing 2017–2023
86Inventor score
Files withIBM15
Top patents by PatentIndex Score
15 records- 0190US10169186B1Efficient testing of direct memory address translationIBM·Filed 2017·Granted Jan 1, 2019·5 cites·15 claims
- 0288US10169185B1Efficient testing of direct memory address translationIBM·Filed 2017·Granted Jan 1, 2019·4 cites·11 claims
- 0374US12130749B2Validation of store coherence relative to page translation invalidationIBM·Filed 2023·Granted Oct 29, 2024·0 cites·20 claims
- 0473US10521355B2Method, system, and apparatus for stress testing memory translation tablesIBM·Filed 2017·Granted Dec 31, 2019·1 cites·20 claims
- 0567US11620235B1Validation of store coherence relative to page translation invalidationIBM·Filed 2021·Granted Apr 4, 2023·0 cites·20 claims
- 0663US11061821B2Method, system, and apparatus for stress testing memory translation tablesIBM·Filed 2019·Granted Jul 13, 2021·0 cites·20 claims
- 0763US10489261B2Efficient testing of direct memory address translationIBM·Filed 2018·Granted Nov 26, 2019·0 cites·16 claims
- 0863US10481991B2Efficient testing of direct memory address translationIBM·Filed 2018·Granted Nov 19, 2019·0 cites·19 claims
- 0961US12450411B2Hazard generating for speculative cores in a microprocessorIBM·Filed 2021·Granted Oct 21, 2025·0 cites·20 claims
- 1053US12141071B2Performance and reliability of processor store operation data transfersIBM·Filed 2022·Granted Nov 12, 2024·0 cites·20 claims
- 1153US12118355B2Cache coherence validation using delayed fulfillment of L2 requestsIBM·Filed 2021·Granted Oct 15, 2024·0 cites·17 claims
- 1249US11094391B2List insertion in test segments with non-naturally aligned data boundariesIBM·Filed 2019·Granted Aug 17, 2021·0 cites·16 claims
- 1348US10748637B2System and method for testing processor errorsIBM·Filed 2018·Granted Aug 18, 2020·0 cites·20 claims
- 1446US10438682B2List insertion in test segments with non-naturally aligned data boundariesIBM·Filed 2017·Granted Oct 8, 2019·0 cites·11 claims
- 1545US11501046B2Pre-silicon chip model of extracted workload inner loop instruction tracesIBM·Filed 2020·Granted Nov 15, 2022·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →