Inventor · disambiguated record
Ngan N. Pham
Also filed as: PHAM NGAN · PHAM NGAN N · PHAM NGAN NGOC
12 granted patents·9 pending applications·71 citations·filing 2005–2009
89Inventor score
Technology areasG06F
Top patents by PatentIndex Score
21 records- 0187US7457920B1Method and system for cache evictionIBM·Filed 2008·Granted Nov 25, 2008·18 cites·1 claims
- 0286US7865669B2System and method for dynamically selecting the fetch path of data for improving processor performanceINTERNAT MACHINES BUSINESS CORP·Filed 2007·Granted Jan 4, 2011·21 cites·9 claims
- 0374US7925838B2Directory-based data transfer protocol for multiprocessor systemIBM·Filed 2008·Granted Apr 12, 2011·6 cites·10 claims
- 0469US7844779B2Method and system for intelligent and dynamic cache replacement management based on efficient use of cache for individual processor coreIBM·Filed 2007·Granted Nov 30, 2010·5 cites·1 claims
- 0567US8996812B2Write-back coherency data cache for resolving read/write conflictsKORNEGAY MARCUS LATHAN·Filed 2009·Granted Mar 31, 2015·6 cites·18 claims
- 0666US8065487B2Structure for shared cache evictionKORNEGAY MARCUS L·Filed 2008·Granted Nov 22, 2011·4 cites·16 claims
- 0763US8195892B2Structure for silent invalid state transition handling in an SMP environmentKORNEGAY MARCUS L·Filed 2008·Granted Jun 5, 2012·3 cites·11 claims
- 0862US7404045B2Directory-based data transfer protocol for multiprocessor systemIBM·Filed 2005·Granted Jul 22, 2008·2 cites·10 claims
- 0961US7840759B2Shared cache evictionIBM·Filed 2007·Granted Nov 23, 2010·2 cites·19 claims
- 1059US8131943B2Structure for dynamic initial cache line coherency state assignment in multi-processor systemsCOLGLAZIER DANIEL J·Filed 2008·Granted Mar 6, 2012·3 cites·8 claims
- 1156US8812793B2Silent invalid state transition handling in an SMP environmentKORNEGAY MARCUS L·Filed 2006·Granted Aug 19, 2014·1 cites·9 claims
- 1248US2010332763A1Apparatus, system, and method for cache coherency eliminationIBM·Filed 2009·Application pending·0 cites
- 1347US2009193196A1Method and system for cache evictionKORNEGAY MARCUS LATHAN·Filed 2008·Application pending·0 cites
- 1444US2008209131A1Structures, systems and arrangements for cache managementKORNEGAY MARCUS L·Filed 2008·Application pending·0 cites
- 1544US2008120469A1Systems and Arrangements for Cache ManagementIBM·Filed 2006·Application pending·0 cites
- 1644US2008201531A1Structure for administering an access conflict in a computer memory cacheKORNEGAY MARCUS L·Filed 2008·Application pending·0 cites
- 1742US8838909B2Dynamic initial cache line coherency state assignment in multi-processor systemsCOLGLAZIER DANIEL J·Filed 2007·Granted Sep 16, 2014·0 cites·18 claims
- 1842US2008140942A1Implementing a hot coherency state to a cache coherency protocol in a symmetric multi-processor environmentKORNEGAY MARCUS L·Filed 2006·Application pending·0 cites
- 1942US2008082755A1Administering An Access Conflict In A Computer Memory CacheKORNEGAY MARCUS L·Filed 2006·Application pending·0 cites
- 2041US2008104323A1Method for identifying, tracking, and storing hot cache lines in an smp environmentCOLGLAZIER DANIEL J·Filed 2006·Application pending·0 cites
- 2141US2007150664A1System and method for default data forwarding coherent caching agentDOMBROWSKI CHRIS·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →